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1. 发明专利

JP2006261668A Split gate type nonvolatile memory device and method for manufacturing the same 审中-公开
标题翻译：分离门型非易失性存储器件及其制造方法
公开(公告)号：JP2006261668A
公开(公告)日：2006-09-28
申请号：JP2006067961
申请日：2006-03-13
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEON HEE-SEOG , KANG SUNG-TAEG , YOON SEUNG-BEOM , HAN JEONG-UK , KIN RYUTAI , SEO BO-YOUNG , KWON HYOK-KI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device and a method for manufacturing the same.
SOLUTION: A split gate memory device of the present invention has a structure in which a floating gate coupling ratio has increased, and as a result, the efficiency and performance of programs and deletion operation are improved.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种非易失性存储装置及其制造方法。解决方案：本发明的分离栅极存储器件具有浮栅耦合比增加的结构，结果提高了程序的效率和性能以及删除操作。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006191049A Nonvolatile memory device, its manufacturing method and its operating method 审中-公开
标题翻译：非易失性存储器件及其制造方法及其操作方法
公开(公告)号：JP2006191049A
公开(公告)日：2006-07-20
申请号：JP2005373219
申请日：2005-12-26
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEON HEE-SEOG , YOON SEUNG-BEOM , HAN JEONG-UK , KIN RYUTAI
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0425 , H01L27/115 , H01L27/11524 , H01L29/42328
摘要： PROBLEM TO BE SOLVED: To disclose a nonvolatile memory device, a method of manufacturing the nonvolatile memory device and a method of operating the same. SOLUTION: This device comprises: a floating gate which is formed on a substrate by interposing a gate insulating film therebetween; a tunnel insulating film which is formed on the floating gate; a selecting gate electrode for inducing an implantation of an electric charge through the gate insulating film; and a controlling gate electrode for inducing a tunneling of an electric charge through the tunnel insulating film. The selecting gate electrode is insulated from the controlling gate electrode. The memory device forms the selecting gate electrode and the controlling gate electrode on the floating gate and can carry out writing and erasing by impressing a voltage to each gate electrode. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：公开非易失性存储器件，非易失性存储器件的制造方法及其操作方法。解决方案：该装置包括：浮置栅极，其通过在其间插入栅极绝缘膜而形成在基板上; 形成在浮动栅上的隧道绝缘膜; 用于通过所述栅极绝缘膜引起电荷的注入的选择栅电极; 以及用于引起电荷穿过隧道绝缘膜的隧穿的控制栅电极。选择栅电极与控制栅电极绝缘。存储器件在浮置栅极上形成选择栅电极和控制栅电极，并且可以通过向每个栅极施加电压来执行写入和擦除。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006032950A Memory device and forming method therefor 审中-公开
标题翻译：存储器件及其形成方法
公开(公告)号：JP2006032950A
公开(公告)日：2006-02-02
申请号：JP2005199340
申请日：2005-07-07
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEON HEE-SEOG , YOON SEUNG-BEOM , HAN JEONG-UK , KIN RYUTAI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/66825 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide an improved method of forming a split-gate memory cell, related to a flash memory device and a forming method therefor. SOLUTION: A method of forming a split-gate self-aligned memory cell comprises a step of forming first and second adjacent floating gates self-aligned to a field oxide region located between them. An oxide film covering the first and the second floating gates and the field oxide region is formed so that the oxide film electrically isolates the first and the second floating gates. A control gate is formed on the oxide film on the first and the second floating gates. A split-gate memory cell formed by the method is also disclosed. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种与闪存器件相关的形成分离栅极存储单元的改进方法及其形成方法。解决方案：形成分裂栅极自对准存储单元的方法包括形成与位于它们之间的场氧化物区域自对准的第一和第二相邻浮置栅极的步骤。形成覆盖第一和第二浮栅和场氧化物区域的氧化膜，使得氧化膜电隔离第一和第二浮栅。控制栅极形成在第一和第二浮栅上的氧化物膜上。还公开了通过该方法形成的分离栅极存储单元。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005322920A Method of manufacturing eeprom cell 审中-公开
标题翻译：制造EEPROM单元的方法
公开(公告)号：JP2005322920A
公开(公告)日：2005-11-17
申请号：JP2005134634
申请日：2005-05-02
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEON HEE-SEOG , YOON SEUNG-BEOM , KIN RYUTAI
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11524 , H01L29/42324 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an EEPROM cell with an improved process of forming a tunnel oxide layer. SOLUTION: The method of manufacturing EEPROM cell includes the steps of: forming a first conductive layer pattern and a tunneling oxide layer, under the first conductive layer pattern; forming a second conductive layer pattern on both sides of the first conductive layer pattern via a gate oxide layer formed on the sidewalls of the first conductive layer pattern and a substrate; then electrically connecting the two patterns to form a conductive layer for a floating gate; forming a coupling oxide layer and a third conductive layer on the conductive layer for a floating gate; and then patterning these layers to create a selected transistor section on the tunneling oxide layer and a control transistor section, wherein the select transistor section has formed a gate stack made up of a selected gate, a first coupling oxide layer pattern and a first floating gate, and the control transistor section has, separated from the select transistor section, a gate stack made up of a control gate, a second coupling oxide layer pattern and a second floating gate. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种通过改进的形成隧道氧化物层的工艺来制造EEPROM电池的方法。解决方案：EEPROM单元的制造方法包括以下步骤：在第一导电层图案下形成第一导电层图案和隧道氧化物层; 通过形成在第一导电层图案和衬底的侧壁上的栅极氧化层，在第一导电层图案的两侧上形成第二导电层图案; 然后电连接两个图案以形成用于浮动栅极的导电层; 在浮栅的导电层上形成耦合氧化物层和第三导电层; 然后对这些层进行构图以在隧道氧化物层和控制晶体管部分上形成选定的晶体管部分，其中选择晶体管部分形成由选择的栅极，第一耦合氧化物层图案和第一浮动栅极构成的栅极堆叠并且控制晶体管部分与选择晶体管部分分离由控制栅极，第二耦合氧化物层图案和第二浮置栅极组成的栅极堆叠。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005268804A Split gate-type nonvolatile semiconductor memory device and manufacturing method of same 有权
标题翻译：分离栅型非易失性半导体存储器件及其制造方法
公开(公告)号：JP2005268804A
公开(公告)日：2005-09-29
申请号：JP2005077986
申请日：2005-03-17
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEON HEE-SEOG , YOON SEUNG-BEOM , KIN RYUTAI , CHOI YONG-SUK
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a split gate-type nonvolatile semiconductor memory device and a manufacturing method of the same.
SOLUTION: A gate insulating layer and a floating gate conductive layer are formed on a semiconductor substrate, a mask layer pattern is formed, a first sacrifice spacer is formed on both walls thereof, an inter-gate insulating layer is formed on the floating gate insulating conductive layer, the first sacrifice spacer is removed, etching is performed on the floating gate conductive layer with the mask layer pattern and inter-gate insulating layer as the masks, a tunneling insulating layer is formed on an exposed portion thereof, a control gate conductive layer is formed on the entire surface of the semiconductor substrate, a second sacrifice spacer is formed thereon, etching is performed on the control gate conductive layer with it as a mask to form the control gate, and etching is performed on the remaining mask layer pattern, inter-gate insulating layer and exposed floating gate conductive layer to form the floating gate.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种分离式栅型非易失性半导体存储器件及其制造方法。解决方案：在半导体衬底上形成栅极绝缘层和浮栅导电层，形成掩模层图案，在其两个壁上形成第一牺牲隔离物，在栅极绝缘层上形成栅极间绝缘层浮置栅极绝缘导电层，去除第一牺牲间隔物，以掩模层图案和栅极间绝缘层为掩模对浮栅导电层进行蚀刻，在其暴露部分上形成隧道绝缘层，控制栅极导电层形成在半导体衬底的整个表面上，在其上形成第二牺牲衬垫，以控制栅极导电层作为掩模进行蚀刻，形成控制栅极，并对剩余的栅极进行蚀刻掩模层图案，栅极间绝缘层和暴露的浮栅导电层以形成浮栅。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2008066725A Eeprom device and method of manufacturing the same 审中-公开
标题翻译： EEPROM装置及其制造方法
公开(公告)号：JP2008066725A
公开(公告)日：2008-03-21
申请号：JP2007226188
申请日：2007-08-31
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK WEON-HO , HAN JEONG-UK , KIN RYUTAI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： PROBLEM TO BE SOLVED: To provide an EEPROM device having improved integration and reliability by a simplified structure, and to provide a method of manufacturing the same. SOLUTION: After forming a tunnel insulating film on a substrate, first and second gate structures having substantially the same structure are formed so as to be mutually isolated from each other on the tunnel insulating film. After forming a common source region on the substrate between the first and second gate structures, first and second drain regions are formed respectively in first and second parts of the substrate adjacent to the first and second gate structures, respectively. Accordingly, functions of a memory transistor and a selection transistor are mutually alternately performed by application of a signal, thus achieving an EEPROM device having first and second transistors of substantially the same structure. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过简化的结构提高集成度和可靠性的EEPROM器件，并提供其制造方法。解决方案：在衬底上形成隧道绝缘膜之后，形成具有基本相同结构的第一和第二栅极结构，以便在隧道绝缘膜上彼此相互隔离。在第一和第二栅极结构之间的衬底上形成公共源极区域之后，分别在衬底的与第一和第二栅极结构相邻的第一和第二部分中分别形成第一和第二漏极区域。因此，存储晶体管和选择晶体管的功能通过施加信号相互交替地执行，从而实现具有基本上相同结构的第一和第二晶体管的EEPROM器件。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2006216957A Semiconductor device having transistor with vertical gate electrode and method of fabricating the same 审中-公开
标题翻译：具有垂直栅极电极的晶体管的半导体器件及其制造方法
公开(公告)号：JP2006216957A
公开(公告)日：2006-08-17
申请号：JP2006026318
申请日：2006-02-02
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KANG SANG-WOO , HAN JEONG-UK , KIN RYUTAI , YOON SEUNG-BEOM
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/785 , H01L27/105 , H01L27/115 , H01L27/228 , H01L27/2436 , H01L29/7881 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having transistor each with a vertical gate electrode and a method of fabricating the same.
SOLUTION: The transistor structure comprises: a semiconductor pattern having first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction; gate patterns disposed adjacent to the first and second sides of the semiconductor pattern; impurity patterns directly contacting the third and fourth sides of the semiconductor pattern; and a gate insulating pattern interposed between the gate patterns and the semiconductor pattern. Since the gate patterns are disposed at side faces of a channel region in this way, a degree of the integration of the semiconductor device can be increased and also a channel width of each transistor can be increased.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有各自具有垂直栅电极的晶体管的半导体器件及其制造方法。解决方案：晶体管结构包括：半导体图案，其具有在横向方向上的第一和第二侧以及面向纵向的第三和第四侧; 邻近半导体图案的第一和第二侧布置的栅极图案; 直接接触半导体图案的第三和第四面的杂质图案; 以及插入在栅极图案和半导体图案之间的栅极绝缘图案。由于栅极图案以这种方式设置在沟道区的侧面，所以可以提高半导体器件的集成度，并且还可以提高每个晶体管的沟道宽度。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005064508A High voltage transistor and manufacturing method therefor 有权
标题翻译：高压晶体管及其制造方法
公开(公告)号：JP2005064508A
公开(公告)日：2005-03-10
申请号：JP2004233400
申请日：2004-08-10
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： YOO TAE-KWANG , JEON HEE-SEOG , YOON SEUNG-BEOM , KIN RYUTAI
IPC分类号： H01L29/41 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792 , H01L31/0328
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/7835
摘要： PROBLEM TO BE SOLVED: To provide a high-voltage transistor for which transistor space can be reduced and a salicide process can be applied, and to provide its manufacturing method.
SOLUTION: This high-voltage transistor is equipped with a channel region formed on a semiconductor substrate, gate insulating film formed on the channel region, lightly-doped source region and lightly-doped drain region formed on the semiconductor substrate through the channel region, heavily-doped source region separated from the channel region by a primary distance, heavily-doped drain region separated from the channel region by a secondary distance which is larger than the primary distance, the gate bottom which is in contact with the gate insulating film on the channel region, the gate electrode formed to be integrated with the gate bottom that has the upper part of the gate extending from the gate bottom and projecting beyond the low concentration drain region by a predetermined length, primary metal silicide layer formed on the heavily-doped source region, and secondary metal silicide layer formed on the heavily-doped drain region.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供可以减小晶体管空间并可以应用自对准硅化物工艺的高压晶体管，并提供其制造方法。解决方案：该高电压晶体管配备有形成在半导体衬底上的沟道区，形成在沟道区上的栅极绝缘膜，通过沟道形成在半导体衬底上的轻掺杂源极区和轻掺杂漏极区区域，重掺杂源极区域与沟道区域分离一次距离，从沟道区域分离出大于主要距离的次级距离的重掺杂漏极区域，与栅极绝缘体接触的栅极底部所述栅电极形成为与所述栅极一体化，所述栅极底部具有从所述栅极底部延伸并突出超过所述低浓度漏极区域预定长度的所述栅极的上部，所述栅极电极形成在所述栅极底部上，重掺杂源极区和形成在重掺杂漏极区上的二次金属硅化物层。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JPH11238816A GATE FORMING METHOD OF SEMICONDUCTOR STORAGE DEVICE PREVENTING CONDUCTIVE LAYER FORMATION IN BOUNDARY REGION 失效
公开(公告)号：JPH11238816A
公开(公告)日：1999-08-31
申请号：JP35679398
申请日：1998-12-15
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIN RYUTAI
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent generation of arc due to polysilicon structures left in a boundary region and prevent polysilicon particle contamination. SOLUTION: A field oxide film 102 is formed on a semiconductor substrate 100 having a cell array region (a) and a boundary region (b) between the cell array region (a) and a peripheral circuit region. A polysilicon layer for forming a floating gate is formed stretching from the cell array region (a) to a part of the boundary region (b), and an insulating layer is formed on the polysilicon layer. A contact gate and a polysilicon layer for forming a single gate are formed on the semiconductor substrate 100, containing the insulating layer. A stack gate and a single gate are formed by cell alignment etching and single gate polyetching, respectively. Polysilicon structures in the boundary region are wholly eliminated by adjusting a cell alignment etching region and a single gate polyetching region.

10. 发明专利

JP2005094007A Partially nitride film sonos device having self-aligned ono structure and manufacturing method of the same 有权
标题翻译：具有自对准结构的部分硝酸盐膜SONOS器件及其制造方法
公开(公告)号：JP2005094007A
公开(公告)日：2005-04-07
申请号：JP2004267186
申请日：2004-09-14
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： JEON HEE-SEOG , YOON SEUNG-BEOM , KIN RYUTAI
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L21/28282 , H01L27/11568 , H01L29/4232 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nitride film SONOS device having a partial length and a forming method of the same. SOLUTION: A control gate 260 comprising the nitride film which is a conductor having the partial length relaxes or prevents the lateral movement of electrons in the control gate 260. Such the structure contains a thin gate oxide film which induces to the device having a low threshold voltage. In addition, the nitride film having the partial length is self-aligned so as to allow the misalignment of the nitride film to be prevented; thereby the movement of the threshold voltage between the devices is decreased. COPYRIGHT: (C)2005,JPO&NCIPI

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