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1. 发明授权

US07709927B2 Shallow trench isolation structures for semiconductor devices including wet etch barriers 有权
标题翻译：用于包括湿蚀刻障碍物的半导体器件的浅沟槽隔离结构
公开(公告)号：US07709927B2
公开(公告)日：2010-05-04
申请号：US12123817
申请日：2008-05-20
申请人： Dong-suk Shin , Il-young Yoon , Yong-kuk Jeong , Jung-shik Heo
发明人： Dong-suk Shin , Il-young Yoon , Yong-kuk Jeong , Jung-shik Heo
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed.
摘要翻译：半导体器件包括覆盖沟槽的内壁，侧壁氧化物层上的氮化物衬垫和填充氮化物衬垫上的沟槽的间隙填充绝缘层的侧壁氧化物层。第一杂质掺杂氧化物层设置在侧壁氧化物层的两个端部的边缘区域处，以便从邻近衬底的上表面的沟槽的入口延伸到氮化物衬垫。凹槽填充绝缘层设置在沟槽中的氮化物衬垫上，以保护第一掺杂杂质的氧化物层的表面。还公开了相关方法。

2. 发明申请

US20080290446A1 SHALLOW TRENCH ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES INCLUDING WET ETCH BARRIERS AND METHODS OF FABRICATING SAME 有权
标题翻译：用于半导体器件的湿式隔离结构，包括湿蚀阻挡层及其制造方法
公开(公告)号：US20080290446A1
公开(公告)日：2008-11-27
申请号：US12123817
申请日：2008-05-20
申请人： Dong-suk Shin , Il-young Yoon , Yong-kuk Jeong , Jung-shik Heo
发明人： Dong-suk Shin , Il-young Yoon , Yong-kuk Jeong , Jung-shik Heo
IPC分类号： H01L23/58 , H01L21/762
CPC分类号： H01L21/76224
摘要： A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed.
摘要翻译：半导体器件包括覆盖沟槽的内壁，侧壁氧化物层上的氮化物衬垫和填充氮化物衬垫上的沟槽的间隙填充绝缘层的侧壁氧化物层。第一杂质掺杂氧化物层设置在侧壁氧化物层的两个端部的边缘区域处，以便从邻近衬底的上表面的沟槽的入口延伸到氮化物衬垫。凹槽填充绝缘层设置在沟槽中的氮化物衬垫上，以保护第一掺杂杂质的氧化物层的表面。还公开了相关方法。

3. 发明申请

US20070037348A1 Method of fabricating trench isolation of semiconductor device 有权
标题翻译：制造半导体器件沟槽隔离的方法
公开(公告)号：US20070037348A1
公开(公告)日：2007-02-15
申请号：US11498667
申请日：2006-08-03
申请人： Dong-suk Shin , Yong-kuk Jeong
发明人： Dong-suk Shin , Yong-kuk Jeong
IPC分类号： H01L21/8242
CPC分类号： H01L21/76224 , C23C16/045 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/31608 , H01L21/31612
摘要： In a method of fabricating a trench isolation structure of a semiconductor device, excellent gap filling properties are attained, without the generation of defects. In one aspect, the method comprises: loading a substrate with a trench formed therein into a high-density plasma (HDP) chemical vapor deposition apparatus; primarily heating the substrate; applying a first bias power to the apparatus so as to form an HDP oxide liner on side wall and bottom surfaces of the trench, a gap remaining in the trench following formation of the HDP oxide liner; removing the application of the first bias power and secondarily heating the substrate; applying a second bias power at a power level that is greater than that of the first bias power to the substrate so as to form an HDP oxide film to fill the gap in the trench; and unloading the substrate from the apparatus.
摘要翻译：在制造半导体器件的沟槽隔离结构的方法中，可以获得良好的间隙填充特性，而不产生缺陷。一方面，该方法包括：将其中形成的沟槽的衬底加载到高密度等离子体（HDP）化学气相沉积设备中; 主要加热基材; 向所述设备施加第一偏置功率以在所述沟槽的侧壁和底表面上形成HDP氧化物衬垫，在所述HDP氧化物衬垫形成之后，留在所述沟槽中的间隙; 去除第一偏置功率的施加并二次加热衬底; 以比所述第一偏置功率大的功率电平对所述衬底施加第二偏置功率以形成HDP氧化物膜以填充所述沟槽中的间隙; 并从该设备卸载该基板。

4. 发明授权

US08237202B2 Semiconductor devices including dehydrogenated interlayer dielectric layers 有权
标题翻译：包括脱氢层间电介质层的半导体器件
公开(公告)号：US08237202B2
公开(公告)日：2012-08-07
申请号：US12987415
申请日：2011-01-10
申请人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
发明人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
IPC分类号： H01L27/118
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/823864 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成NMOS晶体管，在NMOS晶体管上形成第一层间电介质层，并使第一层间电介质层脱氢。使第一层间电介质层脱氢可以改变第一层间电介质层的应力。特别地，第一层间电介质层可以在脱氢后具有200MPa以上的拉伸应力。还提供了包括脱氢层间电介质层的半导体器件。

5. 发明申请

US20110163386A1 Semiconductor Devices Including Dehydrogenated Interlayer Dielectric Layers 有权
标题翻译：包括脱氢层间电介质层的半导体器件
公开(公告)号：US20110163386A1
公开(公告)日：2011-07-07
申请号：US12987415
申请日：2011-01-10
申请人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
发明人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
IPC分类号： H01L27/092 , H01L29/51
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/823864 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成NMOS晶体管，在NMOS晶体管上形成第一层间电介质层，并使第一层间电介质层脱氢。使第一层间电介质层脱氢可以改变第一层间电介质层的应力。特别地，第一层间电介质层可以在脱氢后具有200MPa以上的拉伸应力。还提供了包括脱氢层间电介质层的半导体器件。

6. 发明授权

US07888749B2 Semiconductor devices having selectively tensile stressed gate electrodes and methods of fabricating the same 有权
标题翻译：具有选择性拉伸应力栅电极的半导体器件及其制造方法
公开(公告)号：US07888749B2
公开(公告)日：2011-02-15
申请号：US11752370
申请日：2007-05-23
申请人： Dong-suk Shin , Andrew Tae Kim , Yong-kuk Jeong
发明人： Dong-suk Shin , Andrew Tae Kim , Yong-kuk Jeong
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/823828 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L29/6656 , H01L29/66636 , H01L29/7843 , H01L29/7846
摘要： A semiconductor device includes an active region. A gate electrode is disposed on the active region. An isolation region adjoins the active region, and is recessed with respect to a top surface of the active region underlying the gate electrode. The isolation region may be recessed a depth substantially equal to a height of the gate electrode. In some embodiments, the gate electrode is configured to support current flow through the active region along a first direction, and a tensile stress layer covers the gate electrode and is configured to apply a tensile stress to the gate electrode along a second direction perpendicular to the first direction. The tensile stress layer may cover the recessed isolation region and portions of the active region between the isolation region and the gate electrode. In further embodiments, an interlayer insulating film is disposed on the tensile stress layer and is configured to apply a tensile stress to the gate electrode along the second direction.
摘要翻译：半导体器件包括有源区。栅电极设置在有源区上。隔离区域邻接有源区，并且相对于栅电极下方的有源区的顶表面凹陷。隔离区域可以凹入基本上等于栅电极的高度的深度。在一些实施例中，栅电极被配置为支持沿着第一方向流过有源区的电流，并且拉伸应力层覆盖栅电极，并且构造成沿垂直于第二方向的第二方向向栅电极施加拉伸应力第一个方向拉伸应力层可以覆盖凹陷的隔离区域和隔离区域和栅电极之间的有源区域的部分。在另外的实施例中，层间绝缘膜设置在拉伸应力层上，并被构造成沿着第二方向向栅电极施加拉伸应力。

7. 发明授权

US07608519B2 Method of fabricating trench isolation of semiconductor device 有权
标题翻译：制造半导体器件沟槽隔离的方法
公开(公告)号：US07608519B2
公开(公告)日：2009-10-27
申请号：US11498667
申请日：2006-08-03
申请人： Dong-suk Shin , Yong-kuk Jeong
发明人： Dong-suk Shin , Yong-kuk Jeong
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , C23C16/045 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/31608 , H01L21/31612
摘要： In a method of fabricating a trench isolation structure of a semiconductor device, excellent gap filling properties are attained, without the generation of defects. In one aspect, the method comprises: loading a substrate with a trench formed therein into a high-density plasma (HDP) chemical vapor deposition apparatus; primarily heating the substrate; applying a first bias power to the apparatus so as to form an HDP oxide liner on side wall and bottom surfaces of the trench, a gap remaining in the trench following formation of the HDP oxide liner; removing the application of the first bias power and secondarily heating the substrate; applying a second bias power at a power level that is greater than that of the first bias power to the substrate so as to form an HDP oxide film to fill the gap in the trench; and unloading the substrate from the apparatus.
摘要翻译：在制造半导体器件的沟槽隔离结构的方法中，可以获得良好的间隙填充特性，而不产生缺陷。一方面，该方法包括：将其中形成的沟槽的衬底加载到高密度等离子体（HDP）化学气相沉积设备中; 主要加热基材; 向所述设备施加第一偏置功率以在所述沟槽的侧壁和底表面上形成HDP氧化物衬垫，在所述HDP氧化物衬垫形成之后，留在所述沟槽中的间隙; 去除第一偏置功率的施加并二次加热衬底; 以比所述第一偏置功率大的功率电平对所述衬底施加第二偏置功率以形成HDP氧化物膜以填充所述沟槽中的间隙; 并从该设备卸载该基板。

8. 发明申请

US20080023769A1 Semiconductor Devices Having Selectively Tensile Stressed Gate Electrodes and Methods of Fabricating the Same 有权
标题翻译：具有选择性拉伸的栅极电极的半导体器件及其制造方法
公开(公告)号：US20080023769A1
公开(公告)日：2008-01-31
申请号：US11752370
申请日：2007-05-23
申请人： Dong-suk Shin , Andrew Tae Kim , Yong-kuk Jeong
发明人： Dong-suk Shin , Andrew Tae Kim , Yong-kuk Jeong
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/823828 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L29/6656 , H01L29/66636 , H01L29/7843 , H01L29/7846
摘要： A semiconductor device includes an active region. A gate electrode is disposed on the active region. An isolation region adjoins the active region, and is recessed with respect to a top surface of the active region underlying the gate electrode. The isolation region may be recessed a depth substantially equal to a height of the gate electrode. In some embodiments, the gate electrode is configured to support current flow through the active region along a first direction, and a tensile stress layer covers the gate electrode and is configured to apply a tensile stress to the gate electrode along a second direction perpendicular to the first direction. The tensile stress layer may cover the recessed isolation region and portions of the active region between the isolation region and the gate electrode. In further embodiments, an interlayer insulating film is disposed on the tensile stress layer and is configured to apply a tensile stress to the gate electrode along the second direction.
摘要翻译：半导体器件包括有源区。栅电极设置在有源区上。隔离区域邻接有源区，并且相对于栅电极下方的有源区的顶表面凹陷。隔离区域可以凹入基本上等于栅电极的高度的深度。在一些实施例中，栅电极被配置为支持沿着第一方向流过有源区的电流，并且拉伸应力层覆盖栅电极，并且构造成沿垂直于第二方向的第二方向向栅电极施加拉伸应力第一个方向拉伸应力层可以覆盖凹陷的隔离区域和隔离区域和栅电极之间的有源区域的部分。在另外的实施例中，层间绝缘膜设置在拉伸应力层上，并被构造成沿着第二方向向栅电极施加拉伸应力。

9. 发明申请

US20070105297A1 Semiconductor devices and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070105297A1
公开(公告)日：2007-05-10
申请号：US11593898
申请日：2006-11-07
申请人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
发明人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/823864 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成NMOS晶体管，在NMOS晶体管上形成第一层间电介质层，并使第一层间电介质层脱氢。使第一层间电介质层脱氢可以改变第一层间电介质层的应力。特别地，第一层间电介质层可以在脱氢后具有200MPa以上的拉伸应力。还提供了包括脱氢层间电介质层的半导体器件。

10. 发明授权

US07867867B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07867867B2
公开(公告)日：2011-01-11
申请号：US11593898
申请日：2006-11-07
申请人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
发明人： Yong-kuk Jeong , Andrew-tae Kim , Dong-suk Shin
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/823864 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成NMOS晶体管，在NMOS晶体管上形成第一层间电介质层，并使第一层间电介质层脱氢。使第一层间电介质层脱氢可以改变第一层间电介质层的应力。特别地，第一层间电介质层可以在脱氢后具有200MPa以上的拉伸应力。还提供了包括脱氢层间电介质层的半导体器件。

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