专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5792696A Nonvolatile memory device and manufacturing method thereof 失效
公开(公告)号：US5792696A
公开(公告)日：1998-08-11
申请号：US832339
申请日：1997-04-03
申请人： Dong-jun Kim , Jeong-hyuk Choi , Jeong-hyong Yi
发明人： Dong-jun Kim , Jeong-hyuk Choi , Jeong-hyong Yi
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543 , H01L27/11546
摘要： A nonvolatile memory device and a manufacturing method thereof are provided. The nonvolatile memory device includes memory cells which are formed in a cell array region, peripheral circuit devices which are formed in a peripheral circuit region at the periphery of the cell array region, a field oxide film which is formed between the cell array region and the peripheral circuit region, and a dummy conductive pattern which is formed along and on the field oxide film. Accordingly, damage to the substrate formed between the peripheral circuit region and the cell array region can be reduced, thus a characteristic of insulation between devices can be enhanced.

2. 发明授权

US5932920A Nonvolatile memory device and manufacturing method thereof 失效
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US5932920A
公开(公告)日：1999-08-03
申请号：US633642
申请日：1996-04-17
申请人： Dong-jun Kim , Jeong-hyuk Choi , Jeong-hyong Yi
发明人： Dong-jun Kim , Jeong-hyuk Choi , Jeong-hyong Yi
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543 , H01L27/11546
摘要： A nonvolatile memory device and a manufacturing method thereof are provided. The nonvolatile memory device includes memory cells which are formed in a cell array region, peripheral circuit devices which are formed in a peripheral circuit region at the periphery of the cell array region, a field oxide film which is formed between the cell array region and the peripheral circuit region, and a dummy conductive pattern which is formed along and on the field oxide film. Accordingly, damage to the substrate formed between the peripheral circuit region and the cell array region can be reduced, thus a characteristic of insulation between devices can be enhanced.
摘要翻译：提供了一种非易失性存储器件及其制造方法。非易失性存储器件包括形成在单元阵列区域中的存储单元，形成在单元阵列区域周围的外围电路区域中的外围电路器件，形成在单元阵列区域和外围电路区域和沿着场氧化膜形成的虚设导电图案。因此，可以减少在外围电路区域和电池阵列区域之间形成的衬底的损伤，从而可以提高器件之间的绝缘特性。

3. 发明授权

US5663084A Method for manufacturing nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件的制造方法
公开(公告)号：US5663084A
公开(公告)日：1997-09-02
申请号：US439086
申请日：1995-05-11
申请人： Jeong-hyong Yi , Jeong-hyuk Choi
发明人： Jeong-hyong Yi , Jeong-hyuk Choi
IPC分类号： C23F1/00 , H01L21/318 , H01L21/8238 , H01L21/8247 , H01L27/092 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/11536
摘要： A method for manufacturing a nonvolatile memory device having a memory cell array and a peripheral circuit portion which includes the steps of forming a field oxide film on a semiconductor substrate to form an active region and an isolation region; forming a first dielectric layer on the entire surface of the substrate where the field oxide film is formed; forming a first conductive layer on the dielectric layer; patterning the conductive layer to form a first conductive pattern in the memory cell array and in the peripheral circuit portion; forming a second dielectric layer on the entire surface of the substrate where the first conductive pattern is formed; selectively etching the second dielectric layer, first conductive pattern, and first dielectric layer formed in the peripheral circuit portion to expose the surface of the substrate in the peripheral circuit portion; forming a third dielectric layer on the substrate of the exposed peripheral circuit portion and on the second dielectric layer of the cell array; forming a second conductive layer on the entire surface of the substrate where the third dielectric layer is formed; and patterning the second conductive layer, second dielectric layer, third dielectric layer, and first conductive layer to form a gate electrode in the peripheral circuit portion, and a control gate, a floating gate, and an upper dielectric layer in the cell array.
摘要翻译：一种制造具有存储单元阵列和外围电路部分的非易失性存储器件的方法，包括在半导体衬底上形成场氧化膜以形成有源区和隔离区的步骤; 在形成有场氧化膜的基板的整个表面上形成第一电介质层; 在所述电介质层上形成第一导电层; 图案化导电层以在存储单元阵列和外围电路部分中形成第一导电图案; 在形成所述第一导电图案的所述基板的整个表面上形成第二电介质层; 选择性地蚀刻形成在外围电路部分中的第二电介质层，第一导电图案和第一电介质层，以暴露外围电路部分中的衬底的表面; 在所述暴露的外围电路部分的基板上和所述电池阵列的所述第二电介质层上形成第三电介质层; 在形成有第三介电层的基板的整个表面上形成第二导电层; 以及图案化第二导电层，第二介电层，第三介电层和第一导电层，以在外围电路部分中形成栅电极，以及在电池阵列中的控制栅极，浮动栅极和上电介质层。

4. 发明授权

US6091116A CMOS device and method for manufacturing the same 失效
标题翻译： CMOS器件及其制造方法
公开(公告)号：US6091116A
公开(公告)日：2000-07-18
申请号：US443283
申请日：1995-05-17
申请人： Dong-jun Kim , Jeong-hyuk Choi
发明人： Dong-jun Kim , Jeong-hyuk Choi
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/76
CPC分类号： H01L21/823892 , H01L27/0922
摘要： A CMOS device includes first and second wells formed in first and second regions of a semiconductor substrate, respectively. First and second transistors are formed in the respective wells. A third transistor is formed in a third region of the semiconductor substrate outside of the wells. A first impurity layer is formed in the vicinity of the depletion region of at least one but not more than two of the first, second, and third regions, and a second impurity layer, deeper than the first impurity layer, is formed in the region(s) of the substrate in which the first impurity layer is not formed. A method for manufacturing such a CMOS device enables the punch-through voltage characteristics of the first, second, and third transistors to be optimally different, without requiring any additional, separate mask processing steps.
摘要翻译： CMOS器件分别包括在半导体衬底的第一和第二区域中形成的第一阱和第二阱。第一和第二晶体管形成在相应的阱中。在阱的外部的半导体衬底的第三区域中形成第三晶体管。在第一，第二和第三区域中的至少一个但不多于两个的耗尽区附近形成第一杂质层，并且在该区域中形成比第一杂质层更深的第二杂质层其中不形成第一杂质层的衬底的一个或多个。一种用于制造这种CMOS器件的方法使得第一，第二和第三晶体管的穿通电压特性能够最佳地不同，而不需要任何额外的分开的掩模处理步骤。

5. 发明授权

US5729491A Nonvolatile integrated circuit memory devices having ground interconnect lattices with reduced lateral dimensions 失效
公开(公告)号：US5729491A
公开(公告)日：1998-03-17
申请号：US745731
申请日：1996-11-12
申请人： Dong-jun Kim , Jeong-hyuk Choi
发明人： Dong-jun Kim , Jeong-hyuk Choi
IPC分类号： G11C16/04 , G11C16/30 , H01L27/115 , G11C11/40 , G11C16/06
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/30
摘要： Nonvolatile integrated circuit memory devices having ground interconnect lattices are provided to have reduced lateral dimensions because the ground interconnect lines therein occupy less total area. With respect to integrated circuit memory devices containing NAND strings of EEPROM memory cells, the ground select electrodes for respective first and second pluralities of NAND strings (on a first side of a metal ground line) are joined together so that the number of ground select electrodes crossing the metal ground line can be reduced. The area normally occupied by the crossing ground select electrodes can then be used to interconnect the metal ground line to a substrate ground line using an interconnect via. Thus, the area normally reserved exclusively for the ground interconnect vias can be reduced or eliminated altogether by reducing the number of ground select electrodes which actually cross the metal ground line. In addition, to facilitate the connection of the metal ground line to the substrate ground line, depletion-mode transistors are formed in those areas where the ground select electrode(s) crosses the substrate ground line(s). The use of depletion-mode transistors prevents the formation of an electrical "open" between the substrate ground line and the metal ground line when the ground select electrodes are unbiased.

6. 发明授权

US06406955B1 Method for manufacturing CMOS devices having transistors with mutually different punch-through voltage characteristics 有权
标题翻译：制造具有相互不同的穿通电压特性的晶体管的CMOS器件的方法
公开(公告)号：US06406955B1
公开(公告)日：2002-06-18
申请号：US09566918
申请日：2000-05-09
申请人： Dong-jun Kim , Jeong-hyuk Choi
发明人： Dong-jun Kim , Jeong-hyuk Choi
IPC分类号： H01L218238
CPC分类号： H01L21/823892 , H01L27/0922
摘要： A CMOS device which includes first and second wells formed in first and second regions of a semiconductor substrate, respectively, first and second transistors formed in the respective wells, a third transistor formed in a third region of the semiconductor substrate outside of the wells, a first impurity layer formed in the vicinity of the depletion region of at least one but not more than two of the first, second, and third regions, and a second impurity layer deeper than the first impurity layer and formed in the region(s) of the substrate in which the first impurity layer is not formed. A method for manufacturing such a CMOS device enables the punch-through voltage characteristics of the first, second, and third transistors to be optimally different, without necessitating any additional, separate mask processing steps.
摘要翻译：一种CMOS器件，包括分别形成在半导体衬底的第一和第二区域中的第一和第二阱，分别形成在各个阱中的第一和第二晶体管，形成在所述阱外部的半导体衬底的第三区域中的第三晶体管，形成在第一，第二和第三区域中的至少一个但不多于两个的耗尽区附近的第一杂质层和比第一杂质层更深的第二杂质层，并形成在第一，不形成第一杂质层的基板。制造这种CMOS器件的方法使得第一，第二和第三晶体管的穿透电压特性能够最佳地不同，而不需要任何额外的分开的掩模处理步骤。

7. 发明授权

US5790457A Nonvolatile integrated circuit memory devices having ground interconnect lattices with reduced lateral dimensions 失效
标题翻译：具有具有减小的横向尺寸的接地互连晶格的非易失性集成电路存储器件
公开(公告)号：US5790457A
公开(公告)日：1998-08-04
申请号：US989872
申请日：1997-12-12
申请人： Dong-jun Kim , Jeong-hyuk Choi
发明人： Dong-jun Kim , Jeong-hyuk Choi
IPC分类号： G11C16/04 , G11C16/30 , H01L27/115 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/30
摘要： Nonvolatile integrated circuit memory devices having ground interconnect lattices are provided to have reduced lateral dimensions because the ground interconnect lines therein occupy less total area. With respect to integrated circuit memory devices containing NAND strings of EEPROM memory cells, the ground select electrodes for respective first and second pluralities of NAND strings (on a first side of a metal ground line) are joined together so that the number of ground select electrodes crossing the metal ground line can be reduced. The area normally occupied by the crossing ground select electrodes can then be used to interconnect the metal ground line to a substrate ground line using an interconnect via. Thus, the area normally reserved exclusively for the ground interconnect vias can be reduced or eliminated altogether by reducing the number of ground select electrodes which actually cross the metal ground line. In addition, to facilitate the connection of the metal ground line to the substrate ground line, depletion-mode transistors are formed in those areas where the ground select electrode(s) crosses the substrate ground line(s). The use of depletion-mode transistors prevents the formation of an electrical "open" between the substrate ground line and the metal ground line when the ground select electrodes are unbiased.
摘要翻译：具有接地互连格栅的非易失性集成电路存储器件被提供以具有减小的横向尺寸，因为其中的接地互连线占据较少的总面积。对于包含EEPROM存储单元的NAND串的集成电路存储器件，用于相应的第一和第二多个NAND串（金属接地线的第一侧）的接地选择电极被连接在一起，使得接地选择电极穿过金属接地线可以减少。通常由交叉接地选择电极占据的区域可以用于使用互连通孔将金属接地线与衬底接地线互连。因此，通过减少实际穿过金属接地线的接地选择电极的数量，通常可以减少或消除通常专用于接地互连通孔的区域。此外，为了促进金属接地线与衬底接地线的连接，在接地选择电极与衬底接地线交叉的那些区域中形成耗尽型晶体管。耗尽型晶体管的使用防止了当接地选择电极不偏差时在衬底接地线和金属接地线之间形成电“开路”。

8. 发明授权

US06483749B1 Nonvolatile memory device having bulk bias contact structure in cell array region 有权
标题翻译：在单元阵列区域具有体积偏置接触结构的非易失性存储器件
公开(公告)号：US06483749B1
公开(公告)日：2002-11-19
申请号：US09650493
申请日：2000-08-29
申请人： Jeong-hyuk Choi , Yong-ju Choi , Kyung-joong Joo , Keon-soo Kim
发明人： Jeong-hyuk Choi , Yong-ju Choi , Kyung-joong Joo , Keon-soo Kim
IPC分类号： G11C1604
CPC分类号： H01L27/11526 , G11C16/0416 , H01L27/11521 , H01L27/11536
摘要： A non-volatile memory device including a cell array region formed having a plurality of parallel bit lines, a plurality of parallel word lines, a plurality of memory cells, and a plurality of common source lines, the plurality of bit lines being orthogonal to the plurality of word lines, each of the memory cells being connected to a bit line and a word line and having a stacked gate comprised of a floating gate and a control gate and a source/drain region, the plurality of common source lines being parallel to the plurality of bit lines. The non-volatile memory device also includes a peripheral circuit region for driving the memory cells in the cell array region is formed. The cell array region includes one or more bulk bias contact structures for maintaining the voltage of a bulk region in which the cell array region is formed, at or below a predetermined voltage. The non-volatile memory device can uniformly maintain the voltage of a bulk region regardless of the position of memory cells without increasing the area of a cell array.
摘要翻译：一种非易失性存储器件，包括形成有多个并行位线，多个并行字线，多个存储器单元和多个公共源极线的单元阵列区域，所述多个位线正交于多个字线，每个存储器单元连接到位线和字线，并且具有由浮置栅极和控制栅极以及源极/漏极区域构成的堆叠栅极，所述多个公共源极线平行于多个位线。非易失性存储器件还包括用于驱动单元阵列区域中的存储单元的外围电路区域。电池阵列区域包括一个或多个体积偏置接触结构，用于维持其中形成电池阵列区域的体区的电压，等于或低于预定电压。无论存储器单元的位置如何，非易失性存储器件均可均匀地保持体区的电压，而不增加单元阵列的面积。

9. 发明授权

US5834352A Methods of forming integrated circuits containing high and low voltage field effect transistors therein 失效
标题翻译：在其中形成包含高电压和低电压场效应晶体管的集成电路的方法
公开(公告)号：US5834352A
公开(公告)日：1998-11-10
申请号：US704266
申请日：1996-08-28
申请人： Jeong-hyuk Choi
发明人： Jeong-hyuk Choi
IPC分类号： H01L21/8234 , H01L21/8236
CPC分类号： H01L21/823462
摘要： Methods of forming integrated circuits containing high and low voltage insulated-gate field effect transistors (IGFET) include the steps of forming first and second insulating layers having unequal thicknesses at first and second locations on a face of a semiconductor substrate, respectively, and then forming first and second gate electrodes on the first and second insulating layers, respectively. Formation of the source and drain regions of a high voltage IGFET is then initiated by implanting first dopants of first conductivity type through the first insulating layer and into the first location, using the first gate electrode as an implant mask. Formation of the source and drain regions (e.g., LDD) of the low voltage IGFET is then initiated by implanting second dopants of first conductivity type into the first and second insulating layers. However, the energy level of the implanted second dopants is set at a relatively low level so that the average projection range of the implanted second dopants is greater than the thickness of the second insulating layer, but less than the thickness of the first insulating layer. Thus, negligible quantities of second dopants become implanted into the already partially formed source and drain regions of the high voltage IGFET. This means that the dose level of the implanted first dopants can be preselected to meet the desired breakdown voltage characteristics of the high voltage IGFET, without contamination by the dopants used to subsequently form the low voltage IGFET.
摘要翻译：形成含有高电压和低压绝缘栅场效应晶体管（IGFET）的集成电路的方法包括分别在半导体衬底的表面上的第一和第二位置处形成具有不等厚度的第一绝缘层和第二绝缘层的步骤，然后形成分别在第一和第二绝缘层上的第一和第二栅电极。然后，通过使用第一栅电极作为植入物掩模，通过第一绝缘层注入第一导电类型的第一掺杂剂并进入第一位置来启动高电压IGFET的源极区和漏极区的形成。然后通过将第一导电类型的第二掺杂剂注入第一和第二绝缘层来开始形成低电压IGFET的源区和漏区（例如LDD）。然而，注入的第二掺杂剂的能级设定在相对低的水平，使得注入的第二掺杂剂的平均投影范围大于第二绝缘层的厚度，但小于第一绝缘层的厚度。因此，可忽略量的第二掺杂剂被注入已经部分形成的高压IGFET的源区和漏区。这意味着可以预先选择注入的第一掺杂剂的剂量水平以满足高电压IGFET的期望的击穿电压特性，而不会被用于随后形成低电压IGFET的掺杂剂污染。

10. 发明授权

US5712178A Non-volatile semiconductor memory device and method for manufacturing the same 失效
公开(公告)号：US5712178A
公开(公告)日：1998-01-27
申请号：US477323
申请日：1995-06-07
申请人： Myoung-kwan Cho , Jeong-hyuk Choi
发明人： Myoung-kwan Cho , Jeong-hyuk Choi
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： An EEPROM device in which a high voltage is applied to the chip during the memory cell operation and a method for the manufacturing the same are disclosed. On a P-type semiconductor substrate, a first N-well is formed in a surface portion of the substrate in the cell array region and a second N-well is formed in a first surface of the substrate in the peripheral circuit region. An EEPROM memory cell is formed on the first P-well and a first NMOS transistor is formed on the second P-well. Also, a second NMOS transistor is formed on a second surface portion of the semiconductor substrate in the peripheral circuit 10 region and a PMOS transistor is formed on the second N-well. The impurity concentrations of the first and second P-wells are controlled in accordance with the characteristic of the MOS transistors to be formed. Further, a second NMOS transistor having a resistance against a high voltage is directly formed on the P-type substrate. Thus, the electric characteristic of the EEPROM device is enhanced.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式