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1. 发明授权

US5792696A Nonvolatile memory device and manufacturing method thereof 失效
公开(公告)号：US5792696A
公开(公告)日：1998-08-11
申请号：US832339
申请日：1997-04-03
申请人： Dong-jun Kim , Jeong-hyuk Choi , Jeong-hyong Yi
发明人： Dong-jun Kim , Jeong-hyuk Choi , Jeong-hyong Yi
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543 , H01L27/11546
摘要： A nonvolatile memory device and a manufacturing method thereof are provided. The nonvolatile memory device includes memory cells which are formed in a cell array region, peripheral circuit devices which are formed in a peripheral circuit region at the periphery of the cell array region, a field oxide film which is formed between the cell array region and the peripheral circuit region, and a dummy conductive pattern which is formed along and on the field oxide film. Accordingly, damage to the substrate formed between the peripheral circuit region and the cell array region can be reduced, thus a characteristic of insulation between devices can be enhanced.

2. 发明授权

US5932920A Nonvolatile memory device and manufacturing method thereof 失效
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US5932920A
公开(公告)日：1999-08-03
申请号：US633642
申请日：1996-04-17
申请人： Dong-jun Kim , Jeong-hyuk Choi , Jeong-hyong Yi
发明人： Dong-jun Kim , Jeong-hyuk Choi , Jeong-hyong Yi
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543 , H01L27/11546
摘要： A nonvolatile memory device and a manufacturing method thereof are provided. The nonvolatile memory device includes memory cells which are formed in a cell array region, peripheral circuit devices which are formed in a peripheral circuit region at the periphery of the cell array region, a field oxide film which is formed between the cell array region and the peripheral circuit region, and a dummy conductive pattern which is formed along and on the field oxide film. Accordingly, damage to the substrate formed between the peripheral circuit region and the cell array region can be reduced, thus a characteristic of insulation between devices can be enhanced.
摘要翻译：提供了一种非易失性存储器件及其制造方法。非易失性存储器件包括形成在单元阵列区域中的存储单元，形成在单元阵列区域周围的外围电路区域中的外围电路器件，形成在单元阵列区域和外围电路区域和沿着场氧化膜形成的虚设导电图案。因此，可以减少在外围电路区域和电池阵列区域之间形成的衬底的损伤，从而可以提高器件之间的绝缘特性。

3. 发明授权

US6091116A CMOS device and method for manufacturing the same 失效
标题翻译： CMOS器件及其制造方法
公开(公告)号：US6091116A
公开(公告)日：2000-07-18
申请号：US443283
申请日：1995-05-17
申请人： Dong-jun Kim , Jeong-hyuk Choi
发明人： Dong-jun Kim , Jeong-hyuk Choi
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/76
CPC分类号： H01L21/823892 , H01L27/0922
摘要： A CMOS device includes first and second wells formed in first and second regions of a semiconductor substrate, respectively. First and second transistors are formed in the respective wells. A third transistor is formed in a third region of the semiconductor substrate outside of the wells. A first impurity layer is formed in the vicinity of the depletion region of at least one but not more than two of the first, second, and third regions, and a second impurity layer, deeper than the first impurity layer, is formed in the region(s) of the substrate in which the first impurity layer is not formed. A method for manufacturing such a CMOS device enables the punch-through voltage characteristics of the first, second, and third transistors to be optimally different, without requiring any additional, separate mask processing steps.
摘要翻译： CMOS器件分别包括在半导体衬底的第一和第二区域中形成的第一阱和第二阱。第一和第二晶体管形成在相应的阱中。在阱的外部的半导体衬底的第三区域中形成第三晶体管。在第一，第二和第三区域中的至少一个但不多于两个的耗尽区附近形成第一杂质层，并且在该区域中形成比第一杂质层更深的第二杂质层其中不形成第一杂质层的衬底的一个或多个。一种用于制造这种CMOS器件的方法使得第一，第二和第三晶体管的穿通电压特性能够最佳地不同，而不需要任何额外的分开的掩模处理步骤。

4. 发明授权

US5729491A Nonvolatile integrated circuit memory devices having ground interconnect lattices with reduced lateral dimensions 失效
公开(公告)号：US5729491A
公开(公告)日：1998-03-17
申请号：US745731
申请日：1996-11-12
申请人： Dong-jun Kim , Jeong-hyuk Choi
发明人： Dong-jun Kim , Jeong-hyuk Choi
IPC分类号： G11C16/04 , G11C16/30 , H01L27/115 , G11C11/40 , G11C16/06
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/30
摘要： Nonvolatile integrated circuit memory devices having ground interconnect lattices are provided to have reduced lateral dimensions because the ground interconnect lines therein occupy less total area. With respect to integrated circuit memory devices containing NAND strings of EEPROM memory cells, the ground select electrodes for respective first and second pluralities of NAND strings (on a first side of a metal ground line) are joined together so that the number of ground select electrodes crossing the metal ground line can be reduced. The area normally occupied by the crossing ground select electrodes can then be used to interconnect the metal ground line to a substrate ground line using an interconnect via. Thus, the area normally reserved exclusively for the ground interconnect vias can be reduced or eliminated altogether by reducing the number of ground select electrodes which actually cross the metal ground line. In addition, to facilitate the connection of the metal ground line to the substrate ground line, depletion-mode transistors are formed in those areas where the ground select electrode(s) crosses the substrate ground line(s). The use of depletion-mode transistors prevents the formation of an electrical "open" between the substrate ground line and the metal ground line when the ground select electrodes are unbiased.

5. 发明授权

US06406955B1 Method for manufacturing CMOS devices having transistors with mutually different punch-through voltage characteristics 有权
标题翻译：制造具有相互不同的穿通电压特性的晶体管的CMOS器件的方法
公开(公告)号：US06406955B1
公开(公告)日：2002-06-18
申请号：US09566918
申请日：2000-05-09
申请人： Dong-jun Kim , Jeong-hyuk Choi
发明人： Dong-jun Kim , Jeong-hyuk Choi
IPC分类号： H01L218238
CPC分类号： H01L21/823892 , H01L27/0922
摘要： A CMOS device which includes first and second wells formed in first and second regions of a semiconductor substrate, respectively, first and second transistors formed in the respective wells, a third transistor formed in a third region of the semiconductor substrate outside of the wells, a first impurity layer formed in the vicinity of the depletion region of at least one but not more than two of the first, second, and third regions, and a second impurity layer deeper than the first impurity layer and formed in the region(s) of the substrate in which the first impurity layer is not formed. A method for manufacturing such a CMOS device enables the punch-through voltage characteristics of the first, second, and third transistors to be optimally different, without necessitating any additional, separate mask processing steps.
摘要翻译：一种CMOS器件，包括分别形成在半导体衬底的第一和第二区域中的第一和第二阱，分别形成在各个阱中的第一和第二晶体管，形成在所述阱外部的半导体衬底的第三区域中的第三晶体管，形成在第一，第二和第三区域中的至少一个但不多于两个的耗尽区附近的第一杂质层和比第一杂质层更深的第二杂质层，并形成在第一，不形成第一杂质层的基板。制造这种CMOS器件的方法使得第一，第二和第三晶体管的穿透电压特性能够最佳地不同，而不需要任何额外的分开的掩模处理步骤。

6. 发明授权

US5790457A Nonvolatile integrated circuit memory devices having ground interconnect lattices with reduced lateral dimensions 失效
标题翻译：具有具有减小的横向尺寸的接地互连晶格的非易失性集成电路存储器件
公开(公告)号：US5790457A
公开(公告)日：1998-08-04
申请号：US989872
申请日：1997-12-12
申请人： Dong-jun Kim , Jeong-hyuk Choi
发明人： Dong-jun Kim , Jeong-hyuk Choi
IPC分类号： G11C16/04 , G11C16/30 , H01L27/115 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/30
摘要： Nonvolatile integrated circuit memory devices having ground interconnect lattices are provided to have reduced lateral dimensions because the ground interconnect lines therein occupy less total area. With respect to integrated circuit memory devices containing NAND strings of EEPROM memory cells, the ground select electrodes for respective first and second pluralities of NAND strings (on a first side of a metal ground line) are joined together so that the number of ground select electrodes crossing the metal ground line can be reduced. The area normally occupied by the crossing ground select electrodes can then be used to interconnect the metal ground line to a substrate ground line using an interconnect via. Thus, the area normally reserved exclusively for the ground interconnect vias can be reduced or eliminated altogether by reducing the number of ground select electrodes which actually cross the metal ground line. In addition, to facilitate the connection of the metal ground line to the substrate ground line, depletion-mode transistors are formed in those areas where the ground select electrode(s) crosses the substrate ground line(s). The use of depletion-mode transistors prevents the formation of an electrical "open" between the substrate ground line and the metal ground line when the ground select electrodes are unbiased.
摘要翻译：具有接地互连格栅的非易失性集成电路存储器件被提供以具有减小的横向尺寸，因为其中的接地互连线占据较少的总面积。对于包含EEPROM存储单元的NAND串的集成电路存储器件，用于相应的第一和第二多个NAND串（金属接地线的第一侧）的接地选择电极被连接在一起，使得接地选择电极穿过金属接地线可以减少。通常由交叉接地选择电极占据的区域可以用于使用互连通孔将金属接地线与衬底接地线互连。因此，通过减少实际穿过金属接地线的接地选择电极的数量，通常可以减少或消除通常专用于接地互连通孔的区域。此外，为了促进金属接地线与衬底接地线的连接，在接地选择电极与衬底接地线交叉的那些区域中形成耗尽型晶体管。耗尽型晶体管的使用防止了当接地选择电极不偏差时在衬底接地线和金属接地线之间形成电“开路”。

7. 发明授权

US07421558B2 System controlling interface timing in memory module and related method 有权
标题翻译：内存模块中的系统控制接口时序及相关方法
公开(公告)号：US07421558B2
公开(公告)日：2008-09-02
申请号：US11256108
申请日：2005-10-24
申请人： Hee-joo Choi , Joon-hee Lee , Dong-jun Kim
发明人： Hee-joo Choi , Joon-hee Lee , Dong-jun Kim
IPC分类号： G06F12/06
CPC分类号： G06F13/1689 , G06F13/1694
摘要： A memory system for controlling interface timing in a memory module and a related timing control method are disclosed. The memory system comprises a memory module having a memory module controller configured to control interface timing of a plurality of memory devices in accordance with memory information and memory signal information. The memory information includes memory initialization information and interface timing information for the plurality of memory devices.
摘要翻译：公开了一种用于控制存储器模块中的接口定时的存储系统和相关的定时控制方法。存储器系统包括具有存储器模块控制器的存储器模块，存储器模块控制器被配置为根据存储器信息和存储器信号信息来控制多个存储器件的接口定时。存储器信息包括用于多个存储器件的存储器初始化信息和接口定时信息。

8. 发明申请

US20060090054A1 System controlling interface timing in memory module and related method 有权
标题翻译：内存模块中的系统控制接口时序及相关方法
公开(公告)号：US20060090054A1
公开(公告)日：2006-04-27
申请号：US11256108
申请日：2005-10-24
申请人： Hee-joo Choi , Joon-hee Lee , Dong-jun Kim
发明人： Hee-joo Choi , Joon-hee Lee , Dong-jun Kim
IPC分类号： G06F13/00
CPC分类号： G06F13/1689 , G06F13/1694
摘要： A memory system for controlling interface timing in a memory module and a related timing control method are disclosed. The memory system comprises a memory module having a memory module controller configured to control interface timing of a plurality of memory devices in accordance with memory information and memory signal information. The memory information includes memory initialization information and interface timing information for the plurality of memory devices.
摘要翻译：公开了一种用于控制存储器模块中的接口定时的存储系统和相关的定时控制方法。存储器系统包括具有存储器模块控制器的存储器模块，存储器模块控制器被配置为根据存储器信息和存储器信号信息来控制多个存储器件的接口定时。存储器信息包括用于多个存储器件的存储器初始化信息和接口定时信息。

9. 发明授权

US08396324B2 Image processing method and apparatus for correcting distortion caused by air particles as in fog 有权
标题翻译：用于校正由空气颗粒引起的变形的图像处理方法和装置
公开(公告)号：US08396324B2
公开(公告)日：2013-03-12
申请号：US12436885
申请日：2009-05-07
申请人： Bong-hyup Kang , Dong-jun Kim , Chang-won Jeon , Hanseok Ko
发明人： Bong-hyup Kang , Dong-jun Kim , Chang-won Jeon , Hanseok Ko
IPC分类号： G06K9/40 , H04N5/00
CPC分类号： G06K9/00664 , G06K9/00791 , G06T5/003 , G06T5/008 , G06T5/20 , G06T5/40 , G06T7/13 , G06T2207/10024 , G06T2207/20192 , G06T2207/20224
摘要： Provided are a method and apparatus for processing an image. The method includes receiving a first luminance image of an image including airlight, which is a type of light that occurs in a foggy environment, and generating an airtight map based on a ratio between an average luminance of the first luminance image, and a standard deviation; and removing the airtight by subtracting the airtight map from the first luminance image and outputting a second luminance image. According to the present invention, airlight components may be effectively removed.
摘要翻译：提供了一种用于处理图像的方法和装置。该方法包括接收包括气雾的图像的第一亮度图像，该气泡是在有雾环境中发生的一种类型的光，并且基于第一亮度图像的平均亮度与标准偏差之间的比率产生气密图 ; 通过从第一亮度图像中减去气密图并输出第二亮度图像来去除气密。根据本发明，可以有效地去除气囊部件。

10. 发明申请

US20060104134A1 Semiconductor memory devices incorporating voltage level shifters for controlling a VPP voltage level independently and methods of operating the same 失效
标题翻译：包含用于独立控制VPP电压电平的电压电平移位器的半导体存储器件及其操作方法
公开(公告)号：US20060104134A1
公开(公告)日：2006-05-18
申请号：US11243428
申请日：2005-10-04
申请人： Dong-jun Kim , Hee-joo Choi , Kae-won Ha
发明人： Dong-jun Kim , Hee-joo Choi , Kae-won Ha
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C29/12005
摘要： A voltage level shifter for a semiconductor memory device includes a VPP level control circuit that is configured to detect a VPP voltage and to change the VPP voltage in response to a package burn-in mode signal and a test mode signal independent of at least one direct current voltage generated in response to the package burn-in mode signal.
摘要翻译：用于半导体存储器件的电压电平转换器包括VPP电平控制电路，其被配置为响应于封装老化模式信号和独立于至少一个直接的测试模式信号来检测VPP电压并改变VPP电压响应于封装老化模式信号产生的电流电压。

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