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    • 1. 发明申请
      US20080056048A1 POWER GATING CIRCUIT, SYSTEM ON CHIP CIRCUIT INCLUDING THE SAME AND POWER GATING METHOD 有权
    • POWER GATING CIRCUIT, SYSTEM ON CHIP CIRCUIT INCLUDING THE SAME AND POWER GATING METHOD
    • 功率增益电路，包括其的芯片电路系统和功率增益方法
    • US20080056048A1
    • 2008-03-06
    • US11846677
    • 2007-08-29
    • Dong-Wook Seo , Jong-Hoon Jung , In-Gyu Park , Chan-Ho Lee
    • Dong-Wook Seo , Jong-Hoon Jung , In-Gyu Park , Chan-Ho Lee
    • G11C5/14 , G05F1/00
    • G11C5/14 , H03K19/0016
    • A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.
    • 存储器件的电源门控电路包括电源门控单元和控制单元。 电源门控单元包括并联连接在存储器件的电源电压和内部电源电压总线之间的第一，第二和第三电源门控晶体管。 三个电源门控晶体管依次导通。 第二和第三电源门控晶体管响应于总线的电压增加而依次接通。 当第二和第三功率选通晶体管依次导通时的定时点是基于检测到逐渐增加内部电源电压的电压电平。 第一功率门控晶体管的尺寸可以小于第二功率门控晶体管的尺寸，并且第二功率门控晶体管的尺寸可以小于第三功率门控晶体管的尺寸。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US07782701B2 Power gating circuit, system on chip circuit including the same and power gating method 有权
    • Power gating circuit, system on chip circuit including the same and power gating method
    • 电源门控电路，片上电路包括相同的电源门控方式
    • US07782701B2
    • 2010-08-24
    • US11846677
    • 2007-08-29
    • Dong-Wook Seo , Jong-Hoon Jung , In-Gyu Park , Chan-Ho Lee
    • Dong-Wook Seo , Jong-Hoon Jung , In-Gyu Park , Chan-Ho Lee
    • G11C5/14
    • G11C5/14 , H03K19/0016
    • A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.
    • 存储器件的电源门控电路包括电源门控单元和控制单元。 电源门控单元包括并联连接在存储器件的电源电压和内部电源电压总线之间的第一，第二和第三电源门控晶体管。 三个电源门控晶体管依次导通。 第二和第三电源门控晶体管响应于总线的电压增加而依次接通。 当第二和第三功率选通晶体管依次导通时的定时点是基于检测到逐渐增加内部电源电压的电压电平。 第一功率门控晶体管的尺寸可以小于第二功率门控晶体管的尺寸，并且第二功率门控晶体管的尺寸可以小于第三功率门控晶体管的尺寸。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明申请
      US20100002531A1 Multi-Port Memory Devices Having Clipping Circuits Therein that Inhibit Data Errors During Overlapping Write and Read Operations 有权
    • Multi-Port Memory Devices Having Clipping Circuits Therein that Inhibit Data Errors During Overlapping Write and Read Operations
    • 具有剪切电路的多端口存储器件在重叠写入和读取操作期间抑制数据错误
    • US20100002531A1
    • 2010-01-07
    • US12496976
    • 2009-07-02
    • Chan-Ho Lee , Dong-Wook Seo
    • Chan-Ho Lee , Dong-Wook Seo
    • G11C5/14 , G11C8/16 , G11C8/00
    • G11C8/16
    • An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line.
    • 集成电路器件包括其中具有多端口存储器单元（例如，双端口SRAM单元）的存储器阵列。 该多端口存储单元至少包括第一和第二读/写端口，其可由响应于字线信号的相应存取晶体管（例如，N型MOS晶体管）提供。 第一和第二读/写端口分别电耦合到第一和第二位线。 还提供了第一限幅电路。 第一限幅电路响应于第一写入控制信号。 第一限幅电路被配置为在第一“重叠”操作期间以读取阻断电压偏置第一位线，以将来自第二位线的数据从多端口存储器单元读取数据同时写入多端口存储器单元 到第一个位线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US07894296B2 Multi-port memory devices having clipping circuits therein that inhibit data errors during overlapping write and read operations 有权
    • Multi-port memory devices having clipping circuits therein that inhibit data errors during overlapping write and read operations
    • 其中具有限幅电路的多端口存储器件在重写写入和读取操作期间阻止数据错误
    • US07894296B2
    • 2011-02-22
    • US12496976
    • 2009-07-02
    • Chan-Ho Lee , Dong-Wook Seo
    • Chan-Ho Lee , Dong-Wook Seo
    • G11C7/12
    • G11C8/16
    • An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line.
    • 集成电路器件包括其中具有多端口存储器单元（例如，双端口SRAM单元）的存储器阵列。 该多端口存储单元至少包括第一和第二读/写端口，其可由响应于字线信号的相应存取晶体管（例如，N型MOS晶体管）提供。 第一和第二读/写端口分别电耦合到第一和第二位线。 还提供了第一限幅电路。 第一限幅电路响应于第一写入控制信号。 第一限幅电路被配置为在第一“重叠”操作期间以读取阻断电压偏置第一位线，以将来自第二位线的数据从多端口存储器单元读取数据同时写入多端口存储器单元 到第一个位线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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