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    • 7. 发明授权
    • Power gating circuit, system on chip circuit including the same and power gating method
    • 电源门控电路,片上电路包括相同的电源门控方式
    • US07782701B2
    • 2010-08-24
    • US11846677
    • 2007-08-29
    • Dong-Wook SeoJong-Hoon JungIn-Gyu ParkChan-Ho Lee
    • Dong-Wook SeoJong-Hoon JungIn-Gyu ParkChan-Ho Lee
    • G11C5/14
    • G11C5/14H03K19/0016
    • A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.
    • 存储器件的电源门控电路包括电源门控单元和控制单元。 电源门控单元包括并联连接在存储器件的电源电压和内部电源电压总线之间的第一,第二和第三电源门控晶体管。 三个电源门控晶体管依次导通。 第二和第三电源门控晶体管响应于总线的电压增加而依次接通。 当第二和第三功率选通晶体管依次导通时的定时点是基于检测到逐渐增加内部电源电压的电压电平。 第一功率门控晶体管的尺寸可以小于第二功率门控晶体管的尺寸,并且第二功率门控晶体管的尺寸可以小于第三功率门控晶体管的尺寸。
    • 8. 发明申请
    • Voltage generator and methods thereof
    • 电压发生器及其方法
    • US20070189085A1
    • 2007-08-16
    • US11644895
    • 2006-12-26
    • Hoon-Jin BangHyo-Sang LeeJong-Hoon Jung
    • Hoon-Jin BangHyo-Sang LeeJong-Hoon Jung
    • G11C5/14
    • G11C5/147
    • A voltage generator and methods thereof are provided. The example voltage generator may include a voltage comparison block which generates an output voltage in response to a read command, the output voltage corresponding to a difference between a reference voltage and a determination voltage and a voltage generation block which outputs the determination voltage and a comparison voltage in response to the read command, an inverse read command having a phase opposite that of the read command, a switching pulse signal and the output voltage. A first example method may include outputting a determination voltage and a comparison voltage in response to a read command, an inverse read command having a phase opposite that of the read command, a switching pulse signal and an output voltage, the output voltage generated in response to the read command and corresponding to a difference between the reference voltage and the determination voltage. A second example method may include maintaining a comparison voltage at a first voltage level if a read command is disabled and transitioning the comparison voltage to a second voltage level if the read command is enabled by discharging electric current along a first path, the first path connected to a first node coupled to at least one resistor, and a second path, the second path connected to a second node coupled with a switched capacitor circuit, the switched capacitor circuit including a capacitor which is selectively connected to the second node in response to the enabled read command.
    • 提供电压发生器及其方法。 示例性电压发生器可以包括响应于读命令产生输出电压的电压比较块,对应于参考电压和确定电压之间的差的输出电压和输出确定电压的电压产生块和比较 响应于读取命令的电压,具有与读取命令相反的相位的反相读取命令,切换脉冲信号和输出电压。 第一示例性方法可以包括响应于读取命令输出确定电压和比较电压,具有与读取命令相反的相位的反向读取命令,开关脉冲信号和输出电压,响应中产生的输出电压 到读取命令并且对应于参考电压和确定电压之间的差。 第二示例性方法可以包括:如果禁止读取命令,则将比较电压保持在第一电压电平,并且如果通过沿着第一路径放电电流使读取命令能够使比较电压转变为第二电压电平,则连接的第一路径 耦合到耦合到至少一个电阻器的第一节点和第二路径,所述第二路径连接到与开关电容器电路耦合的第二节点,所述开关电容器电路包括电容器,所述电容器响应于所述电容器选择性地连接到所述第二节点 启用读命令。
    • 9. 发明授权
    • Semiconductor device and test method of testing the same
    • 半导体器件及其测试方法相同
    • US07075838B2
    • 2006-07-11
    • US10756715
    • 2004-01-13
    • Seong-ho JeungJong-hoon Jung
    • Seong-ho JeungJong-hoon Jung
    • G11C29/06G11C29/50G11C11/413G11C8/08
    • G11C29/12G11C11/41G11C2029/1202G11C2029/1802
    • A semiconductor device and a method of testing the semiconductor device are provided. The semiconductor device includes a memory cell array, a sense amplifier, a control circuit, a row decoder, a bitline-pair voltage setting circuit, and a wordline driver. The memory cell array is connected to one of a plurality of wordlines and a plurality of bitline pairs. The memory cell array comprises a plurality of memory cells, wherein each memory cell is connected to one of the plurality of wordlines and the plurality of bitline pairs. The sense amplifier amplifies data read from the memory cell array. The control circuit controls writing/reading of data to/from the memory cell array. The row decoder decodes an address signal and outputs a decoded signal to select one of the plurality of wordlines. The bitline-pair voltage setting circuit sets the voltage of at least one of the plurality of bitline pairs to a bitline test voltage in a test mode. The wordline driver sets the low-level voltages of the plurality of wordlines to a wordline test voltage in the test mode. The wordline test voltage level can be set to be different from the low-level voltage of the plurality of wordlines in a normal operation mode.
    • 提供半导体器件和测试半导体器件的方法。 半导体器件包括存储单元阵列,读出放大器,控制电路,行解码器,位线对电压设置电路和字线驱动器。 存储单元阵列连接到多个字线和多个位线对之一。 存储单元阵列包括多个存储器单元,其中每个存储器单元连接到多个字线和多个位线对之一。 读出放大器放大从存储单元阵列读出的数据。 控制电路控制向/从存储单元阵列写入/读取数据。 行解码器解码地址信号并输出​​解码信号以选择多个字线中的一个。 位线对电压设定电路在测试模式中将多个位线对中的至少一个的电压设置为位线测试电压。 字线驱动器将测试模式中的多个字线的低电平电压设置为字线测试电压。 字线测试电压电平可以被设置为与正常操作模式中的多个字线的低电平电压不同。