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1. 发明授权

US07580313B2 Semiconductor memory device for reducing cell area 有权
标题翻译：用于减少电池面积的半导体存储器件
公开(公告)号：US07580313B2
公开(公告)日：2009-08-25
申请号：US11589038
申请日：2006-10-30
申请人： Dong-Keun Kim , Jae-Jin Lee
发明人： Dong-Keun Kim , Jae-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/18 , G11C2207/105
摘要： A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.
摘要翻译：一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。半导体存储器件包括：具有第一和第二单元区域的单元区域; 多个Y解码器，其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器; 多个第一数据线，用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线，用于传送在第二单元区域的位线读出放大器处感测和放大的数据。

2. 发明申请

US20050249003A1 Semiconductor memory device for reducing cell area 有权
标题翻译：用于减少电池面积的半导体存储器件
公开(公告)号：US20050249003A1
公开(公告)日：2005-11-10
申请号：US11017683
申请日：2004-12-22
申请人： Dong-Keun Kim , Jae-Jin Lee
发明人： Dong-Keun Kim , Jae-Jin Lee
IPC分类号： G11C7/00 , G11C7/10 , G11C7/18
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/18 , G11C2207/105
摘要： Disclosed is a semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas, wherein each cell area is provided with a plurality of cell blocks and a plurality of bit line sense amplifying units; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier, wherein the first IO sense amplifier is disposed at one side of the cell area and the second IO sense amplifier is disposed at the other side of the cell area; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.
摘要翻译：公开了一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。半导体存储器件包括：具有第一和第二单元区域的单元区域，其中每个单元区域设置有多个单元块和多个位线读出放大单元; 多个Y解码器，其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器，其中第一IO读出放大器设置在单元区域的一侧，第二IO读出放大器设置在单元区域的另一侧; 多个第一数据线，用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线，用于传送在第二单元区域的位线读出放大器处感测和放大的数据。

3. 发明授权

US07139211B2 Semiconductor memory device for reducing cell area 有权
公开(公告)号：US07139211B2
公开(公告)日：2006-11-21
申请号：US11017683
申请日：2004-12-22
申请人： Dong-Keun Kim , Jae-Jin Lee
发明人： Dong-Keun Kim , Jae-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/18 , G11C2207/105
摘要： A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.

4. 发明申请

US20070041258A1 Semiconductor memory device for reducing cell area 有权
标题翻译：用于减少电池面积的半导体存储器件
公开(公告)号：US20070041258A1
公开(公告)日：2007-02-22
申请号：US11589038
申请日：2006-10-30
申请人： Dong-Keun Kim , Jae-Jin Lee
发明人： Dong-Keun Kim , Jae-Jin Lee
IPC分类号： G11C7/02
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/18 , G11C2207/105
摘要： A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.
摘要翻译：一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。半导体存储器件包括：具有第一和第二单元区域的单元区域; 多个Y解码器，其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器; 多个第一数据线，用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线，用于传送在第二单元区域的位线读出放大器处感测和放大的数据。

5. 发明授权

US09535834B2 Electronic device including memory arrays with variable resistance storage elements arranged on different sides of a word line driving unit 有权
标题翻译：电子设备包括具有布置在字线驱动单元的不同侧上的可变电阻存储元件的存储器阵列
公开(公告)号：US09535834B2
公开(公告)日：2017-01-03
申请号：US14563645
申请日：2014-12-08
申请人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
发明人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
IPC分类号： G06F12/08 , G11C13/00 , G11C11/4099 , G11C11/16
CPC分类号： G11C13/004 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0207 , G06F12/08 , G06F12/0875 , G06F2212/2024 , G06F2212/452 , G06F2212/60 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C2013/0054 , G11C2213/79 , G11C2213/82
摘要： An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.
摘要翻译：电子设备包括半导体器件，其中半导体器件包括：用于驱动多个字线的字线驱动单元; 布置在字线驱动单元的一侧的第一单元阵列; 布置在所述字线驱动单元的另一侧的第二单元阵列; 布置在所述第一单元阵列和所述第二单元阵列之间的偏置电压产生单元，用于基于流过所述第一单元阵列中包括的所述第一参考电阻元件的电流和所述第二单元中包括的所述第二参考电阻元件来产生偏置电压阵列第一读取控制单元; 和第二读取控制单元。

6. 发明授权

US08089812B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08089812B2
公开(公告)日：2012-01-03
申请号：US11967536
申请日：2007-12-31
申请人： Dong-Keun Kim , Jee-Eun Lee
发明人： Dong-Keun Kim , Jee-Eun Lee
IPC分类号： G11C11/34
CPC分类号： G11C29/808 , G11C29/781 , G11C2029/4402
摘要： A semiconductor memory device can reduce a circuit area necessary for row repair. The semiconductor memory device includes a plurality of memory banks, a plurality of cell arrays arranged in each of the memory banks, a plurality of array word lines arranged in each of the cell arrays, one or more repair word lines arranged in each of the cell arrays, and a plurality of repair information storages configured to store bank information and row addresses of the array word lines to be replaced with the repair word lines.
摘要翻译：半导体存储器件可以减少行修复所需的电路面积。半导体存储器件包括多个存储体，布置在每个存储体中的多个单元阵列，布置在每个单元阵列中的多个阵列字线，布置在每个单元中的一个或多个维修字线阵列和多个修复信息存储器，被配置为存储要由修复字线代替的阵列字线的存储体信息和行地址。

7. 发明申请

US20080080815A1 Optical Connector 有权
标题翻译：光连接器
公开(公告)号：US20080080815A1
公开(公告)日：2008-04-03
申请号：US11571108
申请日：2005-06-20
申请人： Jae-Soo Lee , Hyung-Gon Jeong , Yong-Hyun Kim , Dong-Keun Kim , Yong-Moo Lim , Jeong-Bin Lee , Yong-Woo Yi
发明人： Jae-Soo Lee , Hyung-Gon Jeong , Yong-Hyun Kim , Dong-Keun Kim , Yong-Moo Lim , Jeong-Bin Lee , Yong-Woo Yi
IPC分类号： G02B6/36
CPC分类号： G02B6/3858 , G02B6/3855
摘要： Disclosed herein is an optical connection. In the present invention, an element wire is removably fastened to the optical connector by tightening a main wire connection member using a tightening member from a state in which a plug, a main wire aligning member, a spring, a fastening member, the main wire connection member and the tightening member are previously assembled together. Consequently, only a related optical line need be repaired or replaced with another one, so that the optical line connection work is markedly simplified and can be performed conveniently. Furthermore, there is an advantage of efficient reuse of components.
摘要翻译：本文公开了一种光学连接。在本发明中，通过使用紧固构件从插头，主线对准构件，弹簧，紧固构件，主线等的状态拧紧主线连接构件，将元件线可拆卸地紧固到光连接器连接构件和紧固构件预先组装在一起。因此，仅需要修理或替换相关的光线路，从而显着地简化了光线路连接工作并且可以方便地执行。此外，组件的有效再利用具有优点。

8. 发明申请

US20060091939A1 Power supply circuit of delay locked loop 审中-公开
标题翻译：延迟锁定回路电源电路
公开(公告)号：US20060091939A1
公开(公告)日：2006-05-04
申请号：US11020307
申请日：2004-12-27
申请人： Chang-Ho Do , Dong-Keun Kim
发明人： Chang-Ho Do , Dong-Keun Kim
IPC分类号： G05F1/10
CPC分类号： G05F1/466
摘要： A driving voltage is supplied to a delay locked loop, with having the same voltage level as the power supply voltage but reduced variation and, accordingly, the delay locked loop can be operated more stably. Further, the two different levels of the driving voltage may be provided to the delay locked loop so that various test modes can be provided. The power supply circuit of a delay locked loop includes a voltage comparing unit for comparing the driving voltage with a reference voltage and disabled in response to a selection signal, a driving unit for supplying charges transferred from the power supply voltage into an output terminal so as to increase a voltage level of the driving voltage, in response to the comparison result of the voltage comparing unit; and a control unit for supplying the charges from the driving unit into the output terminal in response to the selection signal, to control the driving voltage to be substantially equal to the power supply voltage.
摘要翻译：驱动电压被提供给延迟锁定环路，其具有与电源电压相同的电压电平，但是减小的变化，因此延迟锁定环路可以更稳定地运行。此外，驱动电压的两个不同级别可以被提供给延迟锁定环，从而可以提供各种测试模式。延迟锁定回路的电源电路包括：电压比较单元，用于将驱动电压与参考电压进行比较，并响应于选择信号而被禁用;驱动单元，用于将从电源电压传送的电荷提供到输出端子，以便响应于电压比较单元的比较结果来增加驱动电压的电压电平; 以及控制单元，用于响应于选择信号将来自驱动单元的电荷提供到输出端，以控制驱动电压基本上等于电源电压。

9. 发明授权

US08592315B2 Chemical mechanical polishing method 有权
标题翻译：化学机械抛光方法
公开(公告)号：US08592315B2
公开(公告)日：2013-11-26
申请号：US12711344
申请日：2010-02-24
申请人： Dong-Keun Kim , Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Dong-Keun Kim , Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： H01L21/302 , H01L21/461 , C23F1/00 , C23F3/00
CPC分类号： H01L21/76819 , C09G1/02 , H01L21/31053
摘要： In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.
摘要翻译：在一个实施方案中，一种用于具有第一层和阶梯部分的基材的化学机械抛光方法。第一层的表面位于台阶部的上表面的上方。通过使用具有自停特性的第一浆料组合物在第一层上进行用于选择性去除台阶部分的抛光工艺，使得第一层变成具有基本平坦表面的第二层。使用不具有自停特性的第二浆料组合物进行第二抛光处理，直到阶梯部分的上表面露出。

10. 发明授权

US07894295B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07894295B2
公开(公告)日：2011-02-22
申请号：US12791032
申请日：2010-06-01
申请人： Dong-Keun Kim , Seung-Lo Kim
发明人： Dong-Keun Kim , Seung-Lo Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C8/06 , G11C8/12
摘要： A semiconductor memory device includes: a reference signal delay unit configured to delay a reference signal for a predetermined operation to output a delayed reference signal; an address delay unit configured to delay a bank address to output a delayed bank address; and a decoding unit configured to receive the delayed reference signal to output a signal for determining a timing of a predetermined operation on a bank selected by the delayed bank address.
摘要翻译：半导体存储器件包括：参考信号延迟单元，被配置为延迟用于预定操作的参考信号以输出延迟的参考信号; 地址延迟单元，配置为延迟存储体地址以输出延迟的存储体地址; 以及解码单元，被配置为接收延迟的参考信号，以输出用于确定由延迟的存储体地址选择的存储体上的预定操作的定时的信号。

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