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1. 发明授权

US08089812B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08089812B2
公开(公告)日：2012-01-03
申请号：US11967536
申请日：2007-12-31
申请人： Dong-Keun Kim , Jee-Eun Lee
发明人： Dong-Keun Kim , Jee-Eun Lee
IPC分类号： G11C11/34
CPC分类号： G11C29/808 , G11C29/781 , G11C2029/4402
摘要： A semiconductor memory device can reduce a circuit area necessary for row repair. The semiconductor memory device includes a plurality of memory banks, a plurality of cell arrays arranged in each of the memory banks, a plurality of array word lines arranged in each of the cell arrays, one or more repair word lines arranged in each of the cell arrays, and a plurality of repair information storages configured to store bank information and row addresses of the array word lines to be replaced with the repair word lines.
摘要翻译：半导体存储器件可以减少行修复所需的电路面积。半导体存储器件包括多个存储体，布置在每个存储体中的多个单元阵列，布置在每个单元阵列中的多个阵列字线，布置在每个单元中的一个或多个维修字线阵列和多个修复信息存储器，被配置为存储要由修复字线代替的阵列字线的存储体信息和行地址。

2. 发明申请

US20090303825A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090303825A1
公开(公告)日：2009-12-10
申请号：US12347547
申请日：2008-12-31
申请人： Dong-Keun KIM , Jee-Eun Lee
发明人： Dong-Keun KIM , Jee-Eun Lee
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/12 , G11C11/4096 , G11C11/4097
摘要： A semiconductor memory device includes a first plurality of banks arranged in a first direction to form a first group of banks; a second plurality of banks arranged in the first direction to form a second group of banks, the first group of banks and the second group of banks arranged in a second direction; a first local data line arranged in the second direction to cross a bank of the second plurality of banks and to transfer input/output data; a second local data line arranged in the second direction to transfer input/output data; a global data line disposed in the first direction that crosses the second direction; and a data exchanger disposed between the second plurality of banks and the global data line for configured to controlling data exchange between the first and second local data lines and the global data line.
摘要翻译：半导体存储器件包括沿第一方向布置的第一组银，以形成第一组堤; 排列在所述第一方向上的第二组银，以形成第二组银行，所述第一组银行和所述第二组银行沿第二方向布置; 布置在所述第二方向上的第一本地数据线，以跨越所述第二多个存储体的存储体并传送输入/输出数据; 沿第二方向布置的用于传送输入/输出数据的第二本地数据线; 设置在与第二方向相交的第一方向上的全局数据线; 以及设置在第二多个存储体之间的数据交换器和全局数据线，用于配置为控制第一和第二本地数据线与全局数据线之间的数据交换。

3. 发明申请

US20100284233A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100284233A1
公开(公告)日：2010-11-11
申请号：US11967536
申请日：2007-12-31
申请人： Dong-Keun Kim , Jee-Eun Lee
发明人： Dong-Keun Kim , Jee-Eun Lee
IPC分类号： G11C29/04 , G11C17/16
CPC分类号： G11C29/808 , G11C29/781 , G11C2029/4402
摘要： A semiconductor memory device can reduce a circuit area necessary for row repair. The semiconductor memory device includes a plurality of memory banks, a plurality of cell arrays arranged in each of the memory banks, a plurality of array word lines arranged in each of the cell arrays, one or more repair word lines arranged in each of the cell arrays, and a plurality of repair information storages configured to store bank information and row addresses of the array word lines to be replaced with the repair word lines.
摘要翻译：半导体存储器件可以减少行修复所需的电路面积。半导体存储器件包括多个存储体，布置在每个存储体中的多个单元阵列，布置在每个单元阵列中的多个阵列字线，布置在每个单元中的一个或多个维修字线阵列和多个修复信息存储器，被配置为存储要由修复字线代替的阵列字线的存储体信息和行地址。

4. 发明申请

US20070069789A1 Flip-flop circuit 审中-公开
标题翻译：触发电路
公开(公告)号：US20070069789A1
公开(公告)日：2007-03-29
申请号：US11529015
申请日：2006-09-27
申请人： Chang-Ho Do , Jee-Eun Lee
发明人： Chang-Ho Do , Jee-Eun Lee
IPC分类号： H03K3/00
CPC分类号： H03K3/356156
摘要： A flip-flop circuit includes a first inverter for inverting a signal of a first node and transferring an inverted signal to a second node, and a second inverter for feeding back a signal of the second node and transferring a feedback signal to the first node. The second inverter includes: a first PMOS transistor and a first NMOS transistor, each gate of which receives the signal of the second node; a second PMOS transistor connected to the first PMOS transistor and having a gate receiving a first voltage, the second PMOS transistor being longer than the first PMOS transistor; and a second NMOS transistor connected to the first NMOS transistor and having a gate receiving a second voltage, the second NMOS transistor being longer than the first NMOS transistor.
摘要翻译：触发器电路包括用于反转第一节点的信号并将反相信号转换到第二节点的第一反相器，以及用于反馈第二节点的信号并将反馈信号传送到第一节点的第二反相器。第二反相器包括：第一PMOS晶体管和第一NMOS晶体管，其每个栅极接收第二节点的信号; 连接到第一PMOS晶体管并且具有接收第一电压的栅极的第二PMOS晶体管，第二PMOS晶体管比第一PMOS晶体管长; 以及连接到第一NMOS晶体管并且具有接收第二电压的栅极的第二NMOS晶体管，所述第二NMOS晶体管比第一NMOS晶体管长。

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