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1. 发明授权

US08804083B2 Liquid crystal display device 有权
标题翻译：液晶显示装置
公开(公告)号：US08804083B2
公开(公告)日：2014-08-12
申请号：US13592525
申请日：2012-08-23
申请人： Kyung-Ho Park , Bo-Yeong Kim , Jae-Won Kim , Byoung-Sun Na , Hyung-Jun Park , Dong-Hyun Yoo , Kye-Uk Lee
发明人： Kyung-Ho Park , Bo-Yeong Kim , Jae-Won Kim , Byoung-Sun Na , Hyung-Jun Park , Dong-Hyun Yoo , Kye-Uk Lee
IPC分类号： G02F1/1343
CPC分类号： G02F1/13624 , G02F1/134336 , G02F1/136209 , G02F1/136286 , G02F1/1368 , G02F2001/134345 , G02F2201/123 , H01L27/1244 , H01L27/1255
摘要： A liquid crystal display device includes upper and lower pixels; gate lines in electrical connection with the adjacent pixels and extending in a row direction, and data lines which cross the gate lines; and a reference voltage line including a vertical portion which passes through the adjacent pixels, and horizontal portions which alternately extend from the vertical portion. Each of the adjacent pixels includes first and second thin film transistors (TFTs) each in electrical connection with a gate line and a data line which correspond to a respective pixel; and a pixel electrode including a first subpixel electrode in connection with an output terminal of the first TFT, and a second subpixel electrode in connection with an output terminal of the second TFT. The horizontal portions of the reference voltage line are in electrical connection with the second subpixel electrodes of the adjacent pixels.
摘要翻译：液晶显示装置包括上下像素; 栅极线与相邻像素电连接并沿行方向延伸，以及跨越栅极线的数据线; 以及包括穿过相邻像素的垂直部分的参考电压线以及从垂直部分交替延伸的水平部分。每个相邻像素包括与栅极线和对应于相应像素的数据线电连接的第一和第二薄膜晶体管（TFT）; 以及与第一TFT的输出端子连接的第一子像素电极和与第二TFT的输出端子连接的第二子像素电极的像素电极。参考电压线的水平部分与相邻像素的第二子像素电极电连接。

2. 发明授权

US08794778B2 Top chassis assembly and display device having the same 有权
标题翻译：顶部底盘组件和显示装置具有相同的功能
公开(公告)号：US08794778B2
公开(公告)日：2014-08-05
申请号：US13608391
申请日：2012-09-10
申请人： Dong-Hyun Yoo , Bo-Yeong Kim , Jae-Won Kim , Kyung-Ho Park , Hyung-Jun Park
发明人： Dong-Hyun Yoo , Bo-Yeong Kim , Jae-Won Kim , Kyung-Ho Park , Hyung-Jun Park
IPC分类号： G09F13/04
CPC分类号： G06F1/16 , G02F1/13452 , G02F2001/13332 , H05K1/118 , H05K3/361 , H05K2201/056 , H05K2201/10128 , H05K2201/10136
摘要： A top chassis assembly includes a top chassis and a contact unit. The top chassis surrounds a non-display area of a display panel. The non-display area includes a pad part through which a signal is provided to the display panel. The contact unit is disposed at an inner surface of the top chassis and contacts the pad part on the non-display area of the display panel.
摘要翻译：顶部底盘组件包括顶部底盘和接触单元。顶部底盘围绕显示面板的非显示区域。非显示区域包括将信号提供给显示面板的焊盘部分。接触单元设置在顶部机架的内表面处，并与显示面板的非显示区域上的焊盘部分接触。

3. 发明授权

US09148148B2 Gate driving circuit and display apparatus having the same 有权
标题翻译：栅极驱动电路及其显示装置
公开(公告)号：US09148148B2
公开(公告)日：2015-09-29
申请号：US13083295
申请日：2011-04-08
申请人： Kyung-Ho Park , Si-Hyun Ahn , Dong-Hee Shin , Hyung-Jun Park , So-Young Kim , Soo-Hyun Kim
发明人： Kyung-Ho Park , Si-Hyun Ahn , Dong-Hee Shin , Hyung-Jun Park , So-Young Kim , Soo-Hyun Kim
IPC分类号： G09G3/00 , H03K19/0185 , G09G3/36
CPC分类号： H03K19/018521 , G09G3/3677 , G09G2310/0286
摘要： Provided is a gate driving circuit including cascade-connected stages that output gate signals. An n-th one of the stages (“n” is a natural number) includes a pull-up part, a pull-up controller, a first pull-down part, a second pull-down part, and a pull-down controller. The pull-up part outputs a first clock signal as an output signal of the n-th stage. The pull-up controller selectively applies first and second powers to a control electrode of the pull-up part. The first pull-down part pulls down a voltage applied to the control electrode of the pull-up part to an off voltage. The second pull-down part pulls down a voltage applied to an output electrode of the pull-up part to the off voltage. The pull-down controller selectively applies the first and second powers to control electrodes of the first and second pull-down parts.
摘要翻译：提供了一种栅极驱动电路，其包括输出栅极信号的级联连接级。第n级（“n”是自然数）包括上拉部分，上拉控制器，第一下拉部分，第二下拉部分和下拉控制器。上拉部分输出第一时钟信号作为第n级的输出信号。上拉控制器选择性地向上拉部分的控制电极施加第一和第二功率。第一下拉部分将施加到上拉部分的控制电极的电压拉低至截止电压。第二下拉部分将施加到上拉部分的输出电极的电压拉低至截止电压。下拉控制器选择性地将第一和第二功率施加到第一和第二下拉部分的控制电极。

4. 发明授权

US08581816B2 Liquid crystal display and driving method thereof 有权
标题翻译：液晶显示及其驱动方法
公开(公告)号：US08581816B2
公开(公告)日：2013-11-12
申请号：US12985404
申请日：2011-01-06
申请人： Kyung-Ho Park , So-Young Kim , Si Hyun Ahn , Dong Hee Shin , Hyung-Jun Park , Soo-Hyun Kim
发明人： Kyung-Ho Park , So-Young Kim , Si Hyun Ahn , Dong Hee Shin , Hyung-Jun Park , Soo-Hyun Kim
IPC分类号： G09G3/34
CPC分类号： G02F1/136213 , G09G3/3648 , G09G3/3677 , G09G2300/0447 , G09G2300/0842 , G09G2310/0205
摘要： A liquid crystal display, the liquid crystal display comprises a plurality of gate lines which includes a first gate line, a transformation gate line, and a second gate line; a data line; and a pixel, wherein the pixel includes a first liquid crystal capacitor which includes a first sub-pixel electrode and a common electrode and a second liquid crystal capacitor which includes a second sub-pixel electrode and a common electrode; a first switching element connected to the first gate line, the data line, and the first sub-pixel electrode; a second switching element connected to the first gate line, the data line, and the second sub-pixel electrode; a third switching element connected to the transformation gate line and the second switching element; a transformation capacitor which includes a first terminal connected to the second gate line and a second terminal connected to the third switching element; and a first period where a gate-on voltage Von is applied to the first gate line and a second period where the gate-on voltage Von is applied to the transformation gate line do not overlap each other and, a gate-off voltage Voff is applied to the second gate line during the second period.
摘要翻译：一种液晶显示器，所述液晶显示器包括多条栅极线，所述栅极线包括第一栅极线，变换栅极线和第二栅极线; 数据线以及像素，其中所述像素包括包括第一子像素电极和公共电极的第一液晶电容器和包括第二子像素电极和公共电极的第二液晶电容器; 连接到第一栅极线，数据线和第一子像素电极的第一开关元件; 连接到第一栅极线，数据线和第二子像素电极的第二开关元件; 连接到变换栅极线和第二开关元件的第三开关元件; 变换电容器，包括连接到第二栅极线的第一端子和连接到第三开关元件的第二端子; 栅极导通电压Von施加到第一栅极线的第一周期和栅极导通电压Von施加到变换栅极线的第二周期彼此不重叠，栅极截止电压Voff为在第二期间施加到第二栅极线。

5. 发明申请

US20120105398A1 GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：闸门驱动电路和显示装置
公开(公告)号：US20120105398A1
公开(公告)日：2012-05-03
申请号：US13083295
申请日：2011-04-08
申请人： Kyung-Ho Park , Si-Hyun Ahn , Dong-Hee Shin , Hyung-Jun Park , So-Young Kim , Soo-Hyun Kim
发明人： Kyung-Ho Park , Si-Hyun Ahn , Dong-Hee Shin , Hyung-Jun Park , So-Young Kim , Soo-Hyun Kim
IPC分类号： G06F3/038 , H03K3/00
CPC分类号： H03K19/018521 , G09G3/3677 , G09G2310/0286
摘要： Provided is a gate driving circuit including cascade-connected stages that output gate signals. An n-th one of the stages (“n” is a natural number) includes a pull-up part, a pull-up controller, a first pull-down part, a second pull-down part, and a pull-down controller. The pull-up part outputs a first clock signal as an output signal of the n-th stage. The pull-up controller selectively applies first and second powers to a control electrode of the pull-up part. The first pull-down part pulls down a voltage applied to the control electrode of the pull-up part to an off voltage. The second pull-down part pulls down a voltage applied to an output electrode of the pull-up part to the off voltage. The pull-down controller selectively applies the first and second powers to control electrodes of the first and second pull-down parts.
摘要翻译：提供了一种栅极驱动电路，其包括输出栅极信号的级联连接级。第n级（“n”是自然数）包括上拉部分，上拉控制器，第一下拉部分，第二下拉部分和下拉控制器。上拉部分输出第一时钟信号作为第n级的输出信号。上拉控制器选择性地向上拉部分的控制电极施加第一和第二功率。第一下拉部分将施加到上拉部分的控制电极的电压拉低至截止电压。第二下拉部分将施加到上拉部分的输出电极的电压拉低至截止电压。下拉控制器选择性地将第一和第二功率施加到第一和第二下拉部分的控制电极。

6. 发明授权

US07211467B2 Method for fabricating leadless packages with mold locking characteristics 有权
标题翻译：用于制造具有模具锁定特性的无引线封装的方法
公开(公告)号：US07211467B2
公开(公告)日：2007-05-01
申请号：US10973385
申请日：2004-10-27
申请人： Sang-Bae Park , Yong-Gill Lee , Hyung-Jun Park , Kyung-Soo Rho , Jin-Hee Won
发明人： Sang-Bae Park , Yong-Gill Lee , Hyung-Jun Park , Kyung-Soo Rho , Jin-Hee Won
IPC分类号： H01L21/00
CPC分类号： H01L24/97 , H01L23/3107 , H01L23/49503 , H01L23/49568 , H01L23/49582 , H01L24/15 , H01L24/48 , H01L2224/0401 , H01L2224/05599 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/13099 , H01L2224/16245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/484 , H01L2224/85399 , H01L2224/85439 , H01L2224/85444 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , H01L2924/01028 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/181 , H01L2924/18301 , H01L2924/351 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A method for fabricating leadless packages with mold locking characteristics is disclosed. A provided leadless leadframe has a plurality of units in a matrix, each unit includes an improved die pad with a plurality of indentations, such as semi-vias in the sidewall thereof and a plurality of leads around the die pad. After chip attachment and electrical connection, a plurality of package bodies for semiconductor packages are individually formed on the corresponding units and covered the indentations in order to enhance the horizontal mold locking capability of the die pad. Using punching, connecting bars of the leadless leadframe are removed to isolate the leadless packages.
摘要翻译：公开了一种用于制造具有锁模特性的无引线封装的方法。提供的无引线框架具有矩阵中的多个单元，每个单元包括具有多个凹口的改进的管芯焊盘，例如其侧壁中的半通孔和围绕管芯焊盘的多个引线。在芯片附接和电连接之后，用于半导体封装的多个封装主体分别形成在相应的单元上并覆盖压痕，以便提高芯片焊盘的水平模具锁定能力。使用无引线框架的冲孔，连接条来拆除无引线封装。

7. 发明申请

US20050258521A1 LEADLESS LEADFRAME WITH AN IMPROVED DIE PAD FOR MOLD LOCKING 有权
标题翻译：无铅LEADFRAME与改进的模具用于模具锁定
公开(公告)号：US20050258521A1
公开(公告)日：2005-11-24
申请号：US10851112
申请日：2004-05-24
申请人： Sang-Bae Park , Yong-Gill Lee , Hyung-Jun Park , Kyung-Soo Rho , Jin-Hee Won
发明人： Sang-Bae Park , Yong-Gill Lee , Hyung-Jun Park , Kyung-Soo Rho , Jin-Hee Won
IPC分类号： H01L21/58 , H01L23/31 , H01L23/495
CPC分类号： H01L24/97 , H01L23/3107 , H01L23/49503 , H01L23/49568 , H01L23/49582 , H01L24/15 , H01L24/48 , H01L2224/0401 , H01L2224/05599 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/13099 , H01L2224/16245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/484 , H01L2224/85399 , H01L2224/85439 , H01L2224/85444 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , H01L2924/01028 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/181 , H01L2924/18301 , H01L2924/351 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A leadless leadframe with an improved die pad for mold locking includes a die pad and a plurality of leads. The leads are arranged around the die pad. A plurality of indentations, such as side semi-vias, are formed on the sidewall of the die pad for filling a package body of the semiconductor package so as to enhance the horizontal mold locking capability of the die pad.
摘要翻译：具有用于模具锁定的改进的芯片焊盘的无引线框架包括芯片焊盘和多个引线。引线布置在管芯焊盘的周围。在管芯焊盘的侧壁上形成多个凹口，例如侧半通孔，用于填充半导体封装的封装体，以增强管芯焊盘的水平模具锁定能力。

8. 发明申请

US20120100049A1 Rare Earth Elements Separation Using Phosphorus Based Adsorbent 有权
标题翻译：使用基于磷的吸附剂进行稀土元素分离
公开(公告)号：US20120100049A1
公开(公告)日：2012-04-26
申请号：US13280280
申请日：2011-10-24
申请人： Lawrence Tavlarides , Hyung-Jun Park
发明人： Lawrence Tavlarides , Hyung-Jun Park
IPC分类号： C01F17/00
CPC分类号： B01J20/3204 , B01J20/103 , B01J20/28083 , B01J20/3248 , B01J20/3257 , C01F17/0006 , C01F17/0075 , C02F1/285 , C02F2101/20 , C02F2209/06
摘要： The present invention relates to methods for the separation of rare earth elements from aqueous solutions and, more particularly, to the separation of lanthanides (e.g., neodymium(III)) from aqueous solutions using an organo phosphorus functionalized adsorbent.
摘要翻译：本发明涉及从水溶液中分离稀土元素的方法，更具体地涉及使用有机磷功能化吸附剂从水溶液中分离镧系元素（例如钕（III））。

9. 发明授权

US07125747B2 Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe 有权
标题翻译：制造无铅半导体封装的方法，包括在无引线框架的矩阵中的电测试
公开(公告)号：US07125747B2
公开(公告)日：2006-10-24
申请号：US10873152
申请日：2004-06-23
申请人： Yong-gill Lee , Hyung-Jun Park , Sang-Bae Park
发明人： Yong-gill Lee , Hyung-Jun Park , Sang-Bae Park
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/568 , H01L21/56 , H01L21/561 , H01L23/3107 , H01L23/3128 , H01L23/49548 , H01L24/48 , H01L24/97 , H01L2224/16245 , H01L2224/48091 , H01L2224/48247 , H01L2224/85001 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2224/85 , H01L2224/81 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A process for manufacturing a plurality of leadless semiconductor packages includes an electrically testing step to test encapsulated chips in a matrix of a leadless leadframe. Firstly, a leadless leadframe having at least a packaging matrix is provided. The packaging matrix defines a plurality of units and a plurality of cutting streets between the units. The leadless leadframe has a plurality of leads in the units and a plurality of connecting bars connecting the leads along the cutting streets. A plated metal layer is formed on the upper surfaces of the leads and the upper surfaces of the connecting bars. After die-attaching, wire-bonding connection, and encapsulation, the leadless leadframe is etched to remove the connecting bars, then two sawing steps are performed. During the first sawing step, the plated metal layer on the upper surface of the connecting bars is cut out to electrically isolate the leads. Therefore, a plurality of chips sealed by an encapsulant on the packaging matrix can be electrically tested by probing which is performed between the first sawing and the second sawing. Thereafter, the encapsulant is cut to form a plurality of individual package bodies of the leadless semiconductor packages during the second sawing.
摘要翻译：一种用于制造多个无引线半导体封装的工艺包括电测试步骤，用于测试无引线框架的矩阵中的封装芯片。首先，提供至少具有封装矩阵的无引线框架。包装矩阵在单元之间定义多个单元和多个切割街道。无引线框架在单元中具有多个引线，并且多个连接条沿着切割街道连接引线。在引线的上表面和连接条的上表面上形成电镀金属层。在裸片安装，引线键合连接和封装之后，对无引线框架进行蚀刻以去除连接条，然后执行两个锯切步骤。在第一锯切步骤期间，切断连接条的上表面上的电镀金属层以使引线电隔离。因此，可以通过在第一锯切和第二锯切之间执行的探测来电测试由包装基质上的密封剂密封的多个芯片。此后，在第二次锯切期间，密封剂被切割以形成多个无引线半导体封装的单个封装体。

10. 发明申请

US20060199308A1 Process for manufacturing sawing type leadless semiconductor packages 审中-公开
标题翻译：制造锯切式无引线半导体封装的工艺
公开(公告)号：US20060199308A1
公开(公告)日：2006-09-07
申请号：US11068799
申请日：2005-03-02
申请人： Yong-Gill Lee , Jin-Young Hong , Hyung-Jun Park , Jin-Hee Won
发明人： Yong-Gill Lee , Jin-Young Hong , Hyung-Jun Park , Jin-Hee Won
IPC分类号： H01L21/50
CPC分类号： H01L21/6835 , H01L21/4828 , H01L21/561 , H01L21/568 , H01L24/97 , H01L2224/48091 , H01L2224/48247 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/18301 , H01L2224/85 , H01L2924/00014 , H01L2924/00012
摘要： A process for manufacturing sawing type leadless semiconductor packages includes a post mold-curing step, which is performed after an encapsulant is formed and after connecting bars of a leadframe are removed. The connecting bars are formed between a plurality of package units of the leadframe to connect a plurality of leads in the package units. After die attachment and electrical connection, the encapsulant is formed over the package units and the connecting bars to encapsulate the chips. The connecting bars are removed prior to the post mold-curing step. Therefore the encapsulant can be cured without deformation or warpage, thereby facilitating the sequent processes.
摘要翻译：一种用于制造锯切型无引线半导体封装件的方法，包括在形成密封剂之后并且在引线框架的连接条被移除之后进行的后模具固化步骤。连接杆形成在引线框架的多个封装单元之间，以连接封装单元中的多个引线。在管芯附接和电连接之后，密封剂形成在封装单元和连接条上以封装芯片。在后模具固化步骤之前移除连接杆。因此，密封剂可以在没有变形或翘曲的情况下固化，从而便于后续处理。

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