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1. 发明申请

US20060214204A1 Ferroelectric structures and devices including upper/lower electrodes of different metals and methods of forming the same 审中-公开
标题翻译：铁电结构和器件包括不同金属的上/下电极及其形成方法
公开(公告)号：US20060214204A1
公开(公告)日：2006-09-28
申请号：US11270730
申请日：2005-11-09
申请人： Dong-Chul Yoo , Byoung Bae , Ji-Eun Lim , Dong-Hyun Im , Myung-Gon Kim
发明人： Dong-Chul Yoo , Byoung Bae , Ji-Eun Lim , Dong-Hyun Im , Myung-Gon Kim
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A ferroelectric capacitor structure can include a ferroelectric layer on a lower electrode and an upper electrode on the ferroelectric layer, the upper electrode including a metal oxide and a metal.
摘要翻译：铁电电容器结构可以包括在下电极上的铁电层和铁电层上的上电极，上电极包括金属氧化物和金属。

2. 发明申请

US20070058415A1 Method for depositing ferroelectric thin films using a mixed oxidant gas 审中-公开
标题翻译：使用混合氧化剂气体沉积铁电薄膜的方法
公开(公告)号：US20070058415A1
公开(公告)日：2007-03-15
申请号：US11520623
申请日：2006-09-14
申请人： Dong-Hyun Im , Byoung-Jae Bae , Ji-Eun Lim , Dong-Chul Yoo , Yeon-Kyu Jung
发明人： Dong-Hyun Im , Byoung-Jae Bae , Ji-Eun Lim , Dong-Chul Yoo , Yeon-Kyu Jung
IPC分类号： G11C11/22
CPC分类号： H01L28/55 , C23C16/409 , H01L27/11502 , H01L28/65
摘要： Disclosed are methods of forming ferroelectric material layers introducing a plurality of metallorganic source compounds into the reaction chamber, the source compounds being supplied in an appropriate ratio for forming the ferroelectric material. These metallorganic source compounds are, in turn, reacted with a NyOx/O2 oxidant gas mixture in which the NyOxcomponent(s) represents at least 50 volume percent of the oxidant gas. This mixture of metallorganic source compounds and oxidant gas mixture(s) are maintained at a deposition temperature and deposition pressure within the reaction chamber suitable for causing a reaction between the metallorganic source compounds and the oxidant gas for a deposition period sufficient to form the ferroelectric material layer. The resulting ferroelectric material layers exhibit improved uniformity, for example, near the interface with the bottom electrode.
摘要翻译：公开了形成将多个金属有机源化合物引入反应室的铁电材料层的方法，以适当的比例供给源化合物以形成铁电体材料。这些金属有机源化合物又与N 2 O 2 O 2 / O 2 O 2氧化剂气体混合物反应，其中N“ y O x分量代表氧化剂气体的至少50体积％。金属有机源化合物和氧化剂气体混合物的混合物保持在反应室内的沉积温度和沉积压力，适于在金属有机源化合物和氧化剂气体之间产生足以形成铁电材料的沉积时间层。所得到的铁电材料层表现出改善的均匀性，例如在与底部电极的界面附近。

3. 发明申请

US20070045689A1 Ferroelectric Structures Including Multilayer Lower Electrodes and Multilayer Upper Electrodes, and Methods of Manufacturing Same 审中-公开
标题翻译：包括多层下电极和多层上电极的铁电结构及其制造方法相同
公开(公告)号：US20070045689A1
公开(公告)日：2007-03-01
申请号：US11460177
申请日：2006-07-26
申请人： Ji-Eun Lim , Dong-Chul Yoo , Byoung-Jae Bae , Dong-Hyun Im , Suk-Pil Kim
发明人： Ji-Eun Lim , Dong-Chul Yoo , Byoung-Jae Bae , Dong-Hyun Im , Suk-Pil Kim
IPC分类号： H01L29/94
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： In a ferroelectric structure after a first lower electrode film is formed using a first metal nitride, a second lower electrode film is formed on the first lower electrode film using a first metal, a second metal oxide and/or a first alloy. After a ferroelectric layer is formed on the second lower electrode film, a first upper electrode film is formed on the ferroelectric layer using a second alloy. Related devices are also disclosed.
摘要翻译：在使用第一金属氮化物形成第一下部电极膜之后的铁电体结构中，使用第一金属，第二金属氧化物和/或第一合金，在第一下部电极膜上形成第二下部电极膜。在第二下电极膜上形成铁电体层之后，使用第二合金在铁电层上形成第一上电极膜。还公开了相关设备。

4. 发明授权

US07583095B2 High-density probe array 失效
标题翻译：高密度探头阵列
公开(公告)号：US07583095B2
公开(公告)日：2009-09-01
申请号：US11464571
申请日：2006-08-15
申请人： Dong-Chul Yoo , Byoung-Jae Bae , Jang-Eun Heo , Ji-Eun Lim , Dong-Hyun Im
发明人： Dong-Chul Yoo , Byoung-Jae Bae , Jang-Eun Heo , Ji-Eun Lim , Dong-Hyun Im
IPC分类号： G01R31/02
CPC分类号： G01R3/00 , Y10T29/49151
摘要： A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.
摘要翻译：可以通过形成设置在牺牲衬底上的探针，在探针上方形成探针衬底，以及去除牺牲衬底来制造探针阵列。在一个实施例中，第一探针可以在牺牲衬底上在行和列方向上二维地形成。可以在布置在行方向上的第一探针之间形成第二探针，使得第一和第二探针之间的距离小于光刻工艺中的分辨率极限。可以在具有第一和第二探针的牺牲衬底上形成探针衬底，并且可以去除牺牲衬底。

5. 发明申请

US20080048226A1 Direct cell via structures for ferroelectric random access memory devices and methods of fabricating such structures 审中-公开
标题翻译：用于铁电随机存取存储器件的直接电池通孔结构以及制造这种结构的方法
公开(公告)号：US20080048226A1
公开(公告)日：2008-02-28
申请号：US11819602
申请日：2007-06-28
申请人： Jang-Eun Heo , Suk-Hun Choi , Dong-Hyun Im , Dong-Chul Yoo , Ik-Soo Kim
发明人： Jang-Eun Heo , Suk-Hun Choi , Dong-Hyun Im , Dong-Chul Yoo , Ik-Soo Kim
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/11507 , H01L27/11502 , H01L28/57
摘要： Provided are FeRAM device constructions and fabrication methods that provide for the direct connection of metal patterns to ferroelectric capacitors. The FeRAM device constructions utilize a combination of one or more barrier layers incorporated in conductive plugs, barrier layers incorporated in primary conductive patterns or conductive patterns formed using one or more noble metals to suppress parametric drift associated with conventional FeRAM constructions.
摘要翻译：提供了FeRAM器件结构和制造方法，其提供金属图案与铁电电容器的直接连接。 FeRAM器件结构利用结合在导电插塞中的一个或多个阻挡层的组合，并入主导电图案中的阻挡层或使用一种或多种贵金属形成的导电图案以抑制与传统FeRAM结构相关的参数漂移。

6. 发明授权

US07585683B2 Methods of fabricating ferroelectric devices 有权
标题翻译：制造铁电体器件的方法
公开(公告)号：US07585683B2
公开(公告)日：2009-09-08
申请号：US11778880
申请日：2007-07-17
申请人： Dong-Hyun Im , Byoung-Jae Bae , Ik-Soo Kim , Jang-Eun Heo , Choong-Man Lee , Dong-Chul Yoo
发明人： Dong-Hyun Im , Byoung-Jae Bae , Ik-Soo Kim , Jang-Eun Heo , Choong-Man Lee , Dong-Chul Yoo
IPC分类号： H01L21/00
CPC分类号： H01L21/02197 , H01L21/02271 , H01L21/02318 , H01L21/31691 , H01L28/55
摘要： A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.
摘要翻译：制造铁电体元件的方法包括在反应室中的基板上形成铁电体层。在反应室中提供惰性气体，同时从其中卸载衬底，从而基本上抑制铁电层上的杂质层的形成。

7. 发明授权

US08703573B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08703573B2
公开(公告)日：2014-04-22
申请号：US13422487
申请日：2012-03-16
申请人： Gyu-Hwan Oh , Dong-Hyun Kim , Kyung-Min Chung , Dong-Hyun Im
发明人： Gyu-Hwan Oh , Dong-Hyun Kim , Kyung-Min Chung , Dong-Hyun Im
IPC分类号： H01L21/20
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L45/1683
摘要： A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other, forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.
摘要翻译：制造半导体器件的方法包括在基片上依次形成第一至第三模层图案并彼此分开，在第一模层图案和第二模层图案之间形成第一半导体图案，以及第二半导体图案，第二模层图案和第三模层图案，通过去除第二模层图案的一部分和第一和第二半导体图案的部分，在第一模层图案和第三模层图案之间形成第一沟槽，用于下电极的材料沿着第一沟槽的侧表面和底表面共形地形成，并且通过移除位于第一和第二半导体图案上的下电极的材料的一部分，分别形成在第一和第二半导体图案上彼此分离的第一和第二下电极第二模层图案。

8. 发明授权

US08680500B2 Phase change memory devices having buried metal silicide patterns 有权
标题翻译：具有埋入金属硅化物图案的相变存储器件
公开(公告)号：US08680500B2
公开(公告)日：2014-03-25
申请号：US13495178
申请日：2012-06-13
申请人： Gyu-Hwan Oh , Byoung-Jae Bae , Dong-Hyun Im , Doo-Hwan Park
发明人： Gyu-Hwan Oh , Byoung-Jae Bae , Dong-Hyun Im , Doo-Hwan Park
IPC分类号： H01L29/02 , H01L47/00 , H01L27/148 , H01L29/768
CPC分类号： H01L45/06 , H01L27/2409 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.
摘要翻译：相变存储器件包括衬底上的杂质区域，有源区域中的杂质区域，至少部分地埋在杂质区域中的金属硅化物图案，杂质区域上的二极管，二极管上的下电极，下电极上的相变层图案，以及相变层图案上的上电极。

9. 发明授权

US08237149B2 Non-volatile memory device having bottom electrode 有权
标题翻译：具有底部电极的非易失性存储器件
公开(公告)号：US08237149B2
公开(公告)日：2012-08-07
申请号：US13087189
申请日：2011-04-14
申请人： Gyu-Hwan Oh , Sug-Woo Jung , Dong-Hyun Im
发明人： Gyu-Hwan Oh , Sug-Woo Jung , Dong-Hyun Im
IPC分类号： H01L47/00 , H01L27/108 , H01L29/94 , H01L31/032
CPC分类号： H01L27/2409 , G11C13/0004 , G11C13/0007 , G11C2213/72 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： Provided is a non-volatile memory device including a bottom electrode disposed on a substrate and having a lower part and an upper part. A conductive spacer is disposed on a sidewall of the lower part of the bottom electrode. A nitride spacer is disposed on a top surface of the conductive spacer and a sidewall of the upper part of the bottom electrode. A resistance changeable element is disposed on the upper part of the bottom electrode and the nitride spacer. The upper part of the bottom electrode contains nitrogen (N).
摘要翻译：提供了一种非易失性存储器件，其包括设置在衬底上并具有下部和上部的底部电极。导电间隔件设置在底部电极的下部的侧壁上。氮化物间隔物设置在导电间隔物的顶表面和底电极的上部的侧壁上。电阻可变元件设置在底部电极和氮化物间隔物的上部。底部电极的上部含有氮（N）。

10. 发明授权

US07838326B2 Methods of fabricating semiconductor device including phase change layer 有权
标题翻译：制造包括相变层的半导体器件的方法
公开(公告)号：US07838326B2
公开(公告)日：2010-11-23
申请号：US12405408
申请日：2009-03-17
申请人： Jin-Il Lee , Sung-Lae Cho , Ik-Soo Kim , Hye-Young Park , Do-Hyung Kim , Dong-Hyun Im
发明人： Jin-Il Lee , Sung-Lae Cho , Ik-Soo Kim , Hye-Young Park , Do-Hyung Kim , Dong-Hyun Im
IPC分类号： H01L21/00
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1616
摘要： Provided are methods of fabricating a semiconductor device including a phase change layer. Methods may include forming a dielectric layer on a substrate, forming an opening in the dielectric layer and depositing, on the substrate having the opening, a phase change layer that contains an element that lowers a process temperature of a thermal treatment process to a temperature that is lower than a melting point of the phase change layer. Methods may include migrating a portion of the phase change layer from outside the opening, into the opening by the thermal treatment process that includes the process temperature that is lower than the melting point of the phase change layer.
摘要翻译：提供制造包括相变层的半导体器件的方法。方法可以包括在衬底上形成电介质层，在电介质层中形成开口，并在具有开口的衬底上沉积相变层，该相变层含有将热处理工艺的工艺温度降低到低于相变层的熔点。方法可以包括通过包括低于相变层的熔点的工艺温度的热处理工艺将一部分相变层从开口外部迁移到开口中。

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