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1. 发明申请

US20120040508A1 Method of Forming Semiconductor Device Having Self-Aligned Plug 有权
标题翻译：形成具有自对准插头的半导体器件的方法
公开(公告)号：US20120040508A1
公开(公告)日：2012-02-16
申请号：US13188981
申请日：2011-07-22
申请人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L47/00
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译：形成基板上的导电图案。形成具有露出导电图案的开口的绝缘层。底部电极形成在导电图案和开口的第一侧壁上。在底部电极和开口的第二侧壁上形成间隔物。间隔件和底部电极形成为低于绝缘层的顶表面。数据存储插头形成在底部电极和间隔件上。数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。在数据存储插头上形成位线。

2. 发明授权

US08680500B2 Phase change memory devices having buried metal silicide patterns 有权
标题翻译：具有埋入金属硅化物图案的相变存储器件
公开(公告)号：US08680500B2
公开(公告)日：2014-03-25
申请号：US13495178
申请日：2012-06-13
申请人： Gyu-Hwan Oh , Byoung-Jae Bae , Dong-Hyun Im , Doo-Hwan Park
发明人： Gyu-Hwan Oh , Byoung-Jae Bae , Dong-Hyun Im , Doo-Hwan Park
IPC分类号： H01L29/02 , H01L47/00 , H01L27/148 , H01L29/768
CPC分类号： H01L45/06 , H01L27/2409 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.
摘要翻译：相变存储器件包括衬底上的杂质区域，有源区域中的杂质区域，至少部分地埋在杂质区域中的金属硅化物图案，杂质区域上的二极管，二极管上的下电极，下电极上的相变层图案，以及相变层图案上的上电极。

3. 发明授权

US08507353B2 Method of forming semiconductor device having self-aligned plug 有权
标题翻译：形成具有自对准插头的半导体器件的方法
公开(公告)号：US08507353B2
公开(公告)日：2013-08-13
申请号：US13188981
申请日：2011-07-22
申请人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L21/20 , H01L21/8244
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译：形成基板上的导电图案。形成具有露出导电图案的开口的绝缘层。底部电极形成在导电图案和开口的第一侧壁上。在底部电极和开口的第二侧壁上形成间隔物。间隔件和底部电极形成为低于绝缘层的顶表面。数据存储插头形成在底部电极和间隔件上。数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。在数据存储插头上形成位线。

4. 发明授权

US09196827B2 Non-volatile memory devices having dual heater configurations and methods of fabricating the same 有权
标题翻译：具有双重加热器配置的非易失性存储器件及其制造方法
公开(公告)号：US09196827B2
公开(公告)日：2015-11-24
申请号：US13547663
申请日：2012-07-12
申请人： Gyu-Hwan Oh , Doo-Hwan Park , Young-Kuk Kim
发明人： Gyu-Hwan Oh , Doo-Hwan Park , Young-Kuk Kim
IPC分类号： H05B3/00 , H01L45/00 , H05B3/14 , H01L27/02 , H01L27/102 , H01L27/24
CPC分类号： H01L45/1233 , H01L27/0296 , H01L27/1021 , H01L27/2409 , H01L45/06 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/145 , H01L45/1683 , H05B3/141
摘要： A non-volatile memory device includes a data storage structure coupled between first and second conductive lines of the memory device. The data storage structure includes a conductive lower heater element, a data storage pattern, and a conductive upper heater element sequentially stacked. At least one sidewall surface of the data storage pattern is coplanar with a sidewall surface of the upper heater element thereabove and a sidewall surface of the lower heater element therebelow. Related fabrication methods are also discussed.
摘要翻译：非易失性存储器件包括耦合在存储器件的第一和第二导线之间的数据存储结构。数据存储结构包括依次堆叠的导电下加热器元件，数据存储模式和导电上加热器元件。数据存储图案的至少一个侧壁表面与上述上加热器元件的侧壁表面和下加热器元件的侧壁表面共面。还讨论了相关的制造方法。

5. 发明授权

US08872148B2 Phase-change memory devices 有权
标题翻译：相变存储器件
公开(公告)号：US08872148B2
公开(公告)日：2014-10-28
申请号：US13735180
申请日：2013-01-07
申请人： Doo-Hwan Park , Gyu-Hwan Oh , Jeong-Min Park , Kyung-Min Chung
发明人： Doo-Hwan Park , Gyu-Hwan Oh , Jeong-Min Park , Kyung-Min Chung
IPC分类号： H01L27/10 , H01L45/00 , H01L27/24
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A phase-change memory device includes a diode, a plug, a doping layer pattern, a phase-change layer pattern and an upper electrode. The diode is disposed on a substrate. The plug is disposed on the diode and has a bottom surface whose area is equal to the area of a top surface of the diode. The plug is formed of metal or a conductive metallic compound. The doping layer pattern is disposed on the plug and has a bottom surface whose area is equal to the area of a top surface of the plug, and includes the same metal or conductive metallic compound as the plug. The phase-change layer pattern is disposed on the doping layer pattern. The upper electrode is disposed on the phase-change layer pattern.
摘要翻译：相变存储器件包括二极管，插头，掺杂层图案，相变层图案和上电极。二极管设置在基板上。插头设置在二极管上，并具有面积等于二极管顶表面面积的底面。插头由金属或导电金属化合物形成。掺杂层图案设置在插塞上，并且具有面积等于插头顶面的面积的底面，并且包括与插头相同的金属或导电金属化合物。相变层图案设置在掺杂层图案上。上电极配置在相变层图案上。

6. 发明申请

US20120252187A1 Semiconductor Device and Method of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120252187A1
公开(公告)日：2012-10-04
申请号：US13422487
申请日：2012-03-16
申请人： Gyu-Hwan Oh , Dong-Hyun Kim , Kyung-Min Chung , Dong-Hyun Im
发明人： Gyu-Hwan Oh , Dong-Hyun Kim , Kyung-Min Chung , Dong-Hyun Im
IPC分类号： H01L21/329 , H01L21/283 , H01L21/02
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L45/1683
摘要： A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.
摘要翻译：制造半导体器件的方法包括在基片上依次形成第一至第三模层图案并彼此分开，在第一模层图案和第二模层图案之间形成第一半导体图案，以及第二半导体图案，第二模层图案和第三模层图案，通过去除第二模层图案的一部分和第一和第二半导体图案的部分，在第一模层图案和第三模层图案之间形成第一沟槽，用于下电极的材料沿着第一沟槽的侧表面和底表面共形地形成，并且通过移除位于第一和第二半导体图案上的下电极的材料的一部分，分别形成在第一和第二半导体图案上彼此分离的第一和第二下电极第二模层图案。

7. 发明授权

US08884263B2 Non-volatile memory device having conductive buffer pattern and method of fabricating the same 有权
标题翻译：具有导电缓冲图案的非易失性存储器件及其制造方法
公开(公告)号：US08884263B2
公开(公告)日：2014-11-11
申请号：US13517755
申请日：2012-06-14
申请人： Gyu-Hwan Oh , Doo-Hwan Park
发明人： Gyu-Hwan Oh , Doo-Hwan Park
IPC分类号： H01L47/00 , H01L27/24 , H01L45/00 , H01L29/06 , H01L27/102
CPC分类号： H01L27/2463 , H01L27/1021 , H01L27/2409 , H01L29/0676 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A diode may be formed within a molding layer on a substrate. A conductive buffer pattern having a greater planar area than the diode may be on the diode and molding layer. An electrode structure may be on the conductive buffer pattern. A data storage pattern may be on the electrode structure. One lateral surface of the conductive buffer pattern may be vertically aligned with one lateral surface of the electrode structure.
摘要翻译：可以在衬底上的模制层内形成二极管。具有比二极管更大的平面面积的导电缓冲图案可以在二极管和模制层上。电极结构可以在导电缓冲图案上。数据存储模式可以在电极结构上。导电缓冲图案的一个侧表面可以与电极结构的一个侧表面垂直对准。

8. 发明授权

US08785213B2 Method of fabricating non-volatile memory device having small contact and related devices 有权
标题翻译：制造具有小接触和相关器件的非易失性存储器件的方法
公开(公告)号：US08785213B2
公开(公告)日：2014-07-22
申请号：US13494206
申请日：2012-06-12
申请人： Gyu-Hwan Oh , Doo-Hwan Park
发明人： Gyu-Hwan Oh , Doo-Hwan Park
IPC分类号： H01L21/00
CPC分类号： H01L45/04 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1253 , H01L45/144 , H01L45/147 , H01L45/1683
摘要： A sacrificial pattern is formed to partially cover the pipe-shaped electrode. A sacrificial spacer is formed on a lateral surface of the sacrificial pattern. The sacrificial spacer extends across the pipe-shaped electrode. The sacrificial spacer has a first side and a second side opposite the first side. The sacrificial pattern is removed to expose the pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer. The pipe-shaped electrode exposed on both sides of the sacrificial spacer may be primarily trimmed. The pipe-shaped electrode is retained under the sacrificial spacer to form a first portion, and a second portion facing the first portion. The second portion of the pipe-shaped electrode is secondarily trimmed. The sacrificial spacer is removed to expose the first portion of the pipe-shaped electrode. A data storage plug is formed on the first portion of the pipe-shaped electrode.
摘要翻译：形成牺牲图案以部分地覆盖管状电极。在牺牲图案的侧表面上形成牺牲隔离物。牺牲隔离物跨越管状电极延伸。牺牲隔离物具有与第一侧相对的第一侧和第二侧。消除牺牲图案以将管状电极暴露在牺牲间隔物的第一和第二侧附近。暴露在牺牲隔离物两侧的管状电极可以主要被修整。管状电极被保持在牺牲隔离物下方以形成第一部分，以及面向第一部分的第二部分。管状电极的第二部分被二次修剪。除去牺牲隔离物以露出管状电极的第一部分。数据存储插头形成在管状电极的第一部分上。

9. 发明授权

US08551805B2 Methods of manufacturing phase-change memory devices 有权
标题翻译：制造相变存储器件的方法
公开(公告)号：US08551805B2
公开(公告)日：2013-10-08
申请号：US13469498
申请日：2012-05-11
申请人： Gyu-Hwan Oh , Doo-Hwan Park , Kyung-Min Chung
发明人： Gyu-Hwan Oh , Doo-Hwan Park , Kyung-Min Chung
IPC分类号： H01L21/00 , H01L21/44 , H01L21/4763 , H01L21/302 , H01L21/461 , H01L41/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L29/861 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase-change memory device includes a word line on a substrate and a phase-change memory cell on the word line and comprising a phase-change material pattern. The device also includes a non-uniform conductivity layer pattern comprising a conductive region on the phase-change material pattern and a non-conductive region contiguous therewith. The device further includes a bit line on the conductive region of the non-uniform conductivity layer pattern. In some embodiments, the phase-change memory cell may further include a diode on the word line, a heating electrode on the diode and wherein the phase-change material layer is disposed on the heating electrode. An ohmic contact layer and a contact plug may be disposed between the diode and the heating electrode.
摘要翻译：相变存储器件包括衬底上的字线和字线上的相变存储器单元，并且包括相变材料图案。该装置还包括不均匀的导电层图案，其包括相变材料图案上的导电区域和与其相邻的非导电区域。该器件还包括位于不均匀导电层图案的导电区上的位线。在一些实施例中，相变存储单元还可以包括字线上的二极管，二极管上的加热电极，并且其中相变材料层设置在加热电极上。欧姆接触层和接触插塞可以设置在二极管和加热电极之间。

10. 发明申请

US20120322223A1 METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICES 有权
标题翻译：制造相变存储器件的方法
公开(公告)号：US20120322223A1
公开(公告)日：2012-12-20
申请号：US13469498
申请日：2012-05-11
申请人： Gyu-Hwan Oh , Doo-Hwan Park , Kyung-Min Chung
发明人： Gyu-Hwan Oh , Doo-Hwan Park , Kyung-Min Chung
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L29/861 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase-change memory device includes a word line on a substrate and a phase-change memory cell on the word line and comprising a phase-change material pattern. The device also includes a non-uniform conductivity layer pattern comprising a conductive region on the phase-change material pattern and a non-conductive region contiguous therewith. The device further includes a bit line on the conductive region of the non-uniform conductivity layer pattern. In some embodiments, the phase-change memory cell may further include a diode on the word line, a heating electrode on the diode and wherein the phase-change material layer is disposed on the heating electrode. An ohmic contact layer and a contact plug may be disposed between the diode and the heating electrode.
摘要翻译：相变存储器件包括衬底上的字线和字线上的相变存储器单元，并且包括相变材料图案。该装置还包括不均匀的导电层图案，其包括相变材料图案上的导电区域和与其相邻的非导电区域。该器件还包括位于不均匀导电层图案的导电区上的位线。在一些实施例中，相变存储单元还可以包括字线上的二极管，二极管上的加热电极，并且其中相变材料层设置在加热电极上。欧姆接触层和接触插塞可以设置在二极管和加热电极之间。

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