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1. 发明申请

US20070045689A1 Ferroelectric Structures Including Multilayer Lower Electrodes and Multilayer Upper Electrodes, and Methods of Manufacturing Same 审中-公开
标题翻译：包括多层下电极和多层上电极的铁电结构及其制造方法相同
公开(公告)号：US20070045689A1
公开(公告)日：2007-03-01
申请号：US11460177
申请日：2006-07-26
申请人： Ji-Eun Lim , Dong-Chul Yoo , Byoung-Jae Bae , Dong-Hyun Im , Suk-Pil Kim
发明人： Ji-Eun Lim , Dong-Chul Yoo , Byoung-Jae Bae , Dong-Hyun Im , Suk-Pil Kim
IPC分类号： H01L29/94
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： In a ferroelectric structure after a first lower electrode film is formed using a first metal nitride, a second lower electrode film is formed on the first lower electrode film using a first metal, a second metal oxide and/or a first alloy. After a ferroelectric layer is formed on the second lower electrode film, a first upper electrode film is formed on the ferroelectric layer using a second alloy. Related devices are also disclosed.
摘要翻译：在使用第一金属氮化物形成第一下部电极膜之后的铁电体结构中，使用第一金属，第二金属氧化物和/或第一合金，在第一下部电极膜上形成第二下部电极膜。在第二下电极膜上形成铁电体层之后，使用第二合金在铁电层上形成第一上电极膜。还公开了相关设备。

2. 发明授权

US07583095B2 High-density probe array 失效
标题翻译：高密度探头阵列
公开(公告)号：US07583095B2
公开(公告)日：2009-09-01
申请号：US11464571
申请日：2006-08-15
申请人： Dong-Chul Yoo , Byoung-Jae Bae , Jang-Eun Heo , Ji-Eun Lim , Dong-Hyun Im
发明人： Dong-Chul Yoo , Byoung-Jae Bae , Jang-Eun Heo , Ji-Eun Lim , Dong-Hyun Im
IPC分类号： G01R31/02
CPC分类号： G01R3/00 , Y10T29/49151
摘要： A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.
摘要翻译：可以通过形成设置在牺牲衬底上的探针，在探针上方形成探针衬底，以及去除牺牲衬底来制造探针阵列。在一个实施例中，第一探针可以在牺牲衬底上在行和列方向上二维地形成。可以在布置在行方向上的第一探针之间形成第二探针，使得第一和第二探针之间的距离小于光刻工艺中的分辨率极限。可以在具有第一和第二探针的牺牲衬底上形成探针衬底，并且可以去除牺牲衬底。

3. 发明申请

US20070058415A1 Method for depositing ferroelectric thin films using a mixed oxidant gas 审中-公开
标题翻译：使用混合氧化剂气体沉积铁电薄膜的方法
公开(公告)号：US20070058415A1
公开(公告)日：2007-03-15
申请号：US11520623
申请日：2006-09-14
申请人： Dong-Hyun Im , Byoung-Jae Bae , Ji-Eun Lim , Dong-Chul Yoo , Yeon-Kyu Jung
发明人： Dong-Hyun Im , Byoung-Jae Bae , Ji-Eun Lim , Dong-Chul Yoo , Yeon-Kyu Jung
IPC分类号： G11C11/22
CPC分类号： H01L28/55 , C23C16/409 , H01L27/11502 , H01L28/65
摘要： Disclosed are methods of forming ferroelectric material layers introducing a plurality of metallorganic source compounds into the reaction chamber, the source compounds being supplied in an appropriate ratio for forming the ferroelectric material. These metallorganic source compounds are, in turn, reacted with a NyOx/O2 oxidant gas mixture in which the NyOxcomponent(s) represents at least 50 volume percent of the oxidant gas. This mixture of metallorganic source compounds and oxidant gas mixture(s) are maintained at a deposition temperature and deposition pressure within the reaction chamber suitable for causing a reaction between the metallorganic source compounds and the oxidant gas for a deposition period sufficient to form the ferroelectric material layer. The resulting ferroelectric material layers exhibit improved uniformity, for example, near the interface with the bottom electrode.
摘要翻译：公开了形成将多个金属有机源化合物引入反应室的铁电材料层的方法，以适当的比例供给源化合物以形成铁电体材料。这些金属有机源化合物又与N 2 O 2 O 2 / O 2 O 2氧化剂气体混合物反应，其中N“ y O x分量代表氧化剂气体的至少50体积％。金属有机源化合物和氧化剂气体混合物的混合物保持在反应室内的沉积温度和沉积压力，适于在金属有机源化合物和氧化剂气体之间产生足以形成铁电材料的沉积时间层。所得到的铁电材料层表现出改善的均匀性，例如在与底部电极的界面附近。

4. 发明授权

US07585683B2 Methods of fabricating ferroelectric devices 有权
标题翻译：制造铁电体器件的方法
公开(公告)号：US07585683B2
公开(公告)日：2009-09-08
申请号：US11778880
申请日：2007-07-17
申请人： Dong-Hyun Im , Byoung-Jae Bae , Ik-Soo Kim , Jang-Eun Heo , Choong-Man Lee , Dong-Chul Yoo
发明人： Dong-Hyun Im , Byoung-Jae Bae , Ik-Soo Kim , Jang-Eun Heo , Choong-Man Lee , Dong-Chul Yoo
IPC分类号： H01L21/00
CPC分类号： H01L21/02197 , H01L21/02271 , H01L21/02318 , H01L21/31691 , H01L28/55
摘要： A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.
摘要翻译：制造铁电体元件的方法包括在反应室中的基板上形成铁电体层。在反应室中提供惰性气体，同时从其中卸载衬底，从而基本上抑制铁电层上的杂质层的形成。

5. 发明申请

US20080020489A1 METHODS OF FABRICATING FERROELECTRIC DEVICES 有权
标题翻译：制造电磁装置的方法
公开(公告)号：US20080020489A1
公开(公告)日：2008-01-24
申请号：US11778880
申请日：2007-07-17
申请人： Dong Hyun Im , Byoung-Jae Bae , Ik-Soo Kim , Jang-Eun Heo , Choong-Man Lee , Dong-Chul Yoo
发明人： Dong Hyun Im , Byoung-Jae Bae , Ik-Soo Kim , Jang-Eun Heo , Choong-Man Lee , Dong-Chul Yoo
IPC分类号： H01L21/00
CPC分类号： H01L21/02197 , H01L21/02271 , H01L21/02318 , H01L21/31691 , H01L28/55
摘要： A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.
摘要翻译：制造铁电体元件的方法包括在反应室中的基板上形成铁电体层。在反应室中提供惰性气体，同时从其中卸载衬底，从而基本上抑制铁电层上的杂质层的形成。

6. 发明授权

US08680500B2 Phase change memory devices having buried metal silicide patterns 有权
标题翻译：具有埋入金属硅化物图案的相变存储器件
公开(公告)号：US08680500B2
公开(公告)日：2014-03-25
申请号：US13495178
申请日：2012-06-13
申请人： Gyu-Hwan Oh , Byoung-Jae Bae , Dong-Hyun Im , Doo-Hwan Park
发明人： Gyu-Hwan Oh , Byoung-Jae Bae , Dong-Hyun Im , Doo-Hwan Park
IPC分类号： H01L29/02 , H01L47/00 , H01L27/148 , H01L29/768
CPC分类号： H01L45/06 , H01L27/2409 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A phase change memory device includes an impurity region on a substrate, the impurity region being in an active region, a metal silicide pattern at least partially buried in the impurity region, a diode on the impurity region, a lower electrode on the diode, a phase change layer pattern on the lower electrode, and an upper electrode on the phase change layer pattern.
摘要翻译：相变存储器件包括衬底上的杂质区域，有源区域中的杂质区域，至少部分地埋在杂质区域中的金属硅化物图案，杂质区域上的二极管，二极管上的下电极，下电极上的相变层图案，以及相变层图案上的上电极。

7. 发明授权

US07759667B2 Phase change memory device including resistant material 失效
标题翻译：相变记忆装置，包括耐磨材料
公开(公告)号：US07759667B2
公开(公告)日：2010-07-20
申请号：US11762801
申请日：2007-06-14
申请人： Young-Lim Park , Sung-Lae Cho , Byoung-Jae Bae , Jin-il Lee , Hye-Young Park , Ji-Eun Lim
发明人： Young-Lim Park , Sung-Lae Cho , Byoung-Jae Bae , Jin-il Lee , Hye-Young Park , Ji-Eun Lim
IPC分类号： H01L29/04
CPC分类号： H01L45/148 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/124 , H01L45/144 , H01L45/1691
摘要： A phase change memory device includes a lower electrode provided on a substrate, an interlayer insulating layer including a contact hole exposing the lower electrode, and covering the substrate, a resistant material pattern filling the contact hole, a phase change pattern interposed between the resistant material pattern and the interlayer insulating layer, and extending between the resistant material pattern and the lower electrode, wherein the resistant material pattern has a higher resistance than the phase change pattern, and an upper electrode in contact with the phase change pattern, the upper electrode being electrically connected to the lower electrode through the phase change pattern.
摘要翻译：相变存储器件包括设置在基板上的下电极，包括暴露下电极的接触孔并覆盖基板的层间绝缘层，填充接触孔的电阻材料图案，插入在电阻材料之间的相变图案图案和层间绝缘层，并且在电阻材料图案和下电极之间延伸，其中电阻材料图案具有比相变图案更高的电阻，以及与相变图案接触的上电极，上电极为通过相变图案电连接到下电极。

8. 发明申请

US20060174827A1 Apparatus for manufacturing semiconductor device 审中-公开
标题翻译：半导体器件制造装置
公开(公告)号：US20060174827A1
公开(公告)日：2006-08-10
申请号：US11329451
申请日：2006-01-10
申请人： Byoung-Jae Bae , Ji-Eun Lim , Yeon-Kyu Jung
发明人： Byoung-Jae Bae , Ji-Eun Lim , Yeon-Kyu Jung
IPC分类号： C30B11/00
CPC分类号： C23C16/45589 , C23C16/45563 , C23C16/45565 , C23C16/45591 , C30B35/00 , Y10T117/10
摘要： A deposition apparatus is provided that has a reaction-chamber, a wafer support, gas supply line, an ejection unit and a diffusion unit. The ejection unit includes a bottom portion spaced apart from a top wall of the reaction chamber to form a space. The diffusion unit is positioned below the gas supply line and includes a planar portion having upwardly extending flanges forming an upwardly open space below the gas supply line. Gas flowing from the gas supply line flows into the upwardly open space and ascends the upwardly extending flanges to diffuse the gas into the space.
摘要翻译：提供一种沉积设备，其具有反应室，晶片支撑件，气体供应管线，喷射单元和扩散单元。喷射单元包括与反应室的顶壁间隔开的底部，以形成空间。扩散单元位于气体供应管线的下方并且包括具有向上延伸的凸缘的平面部分，其在气体供应管线下方形成向上开放的空间。从气体供应管线流出的气体流入向上开放的空间并向上延伸的凸缘上升，以将气体扩散到空间中。

9. 发明申请

US20080054244A1 PHASE CHANGE MEMORY DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20080054244A1
公开(公告)日：2008-03-06
申请号：US11697230
申请日：2007-04-05
申请人： Jin-Il Lee , Ji-Eun Lim , Hye-Young Park , Sung-Lae Cho , Eun-Ae Chung , Ki-Vin Im , Byoung-Jae Bae , Young-Lim Park
发明人： Jin-Il Lee , Ji-Eun Lim , Hye-Young Park , Sung-Lae Cho , Eun-Ae Chung , Ki-Vin Im , Byoung-Jae Bae , Young-Lim Park
IPC分类号： H01L29/02
CPC分类号： H01L45/1616 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： In one embodiment, a phase change memory device includes an insulation structure over a substrate. The insulation structure ahs an opening defined therethrough. A first layer pattern is formed on sidewalls and a bottom of the opening. A second layer pattern is formed on the first layer pattern and substantially fills the opening.
摘要翻译：在一个实施例中，相变存储器件包括在衬底上的绝缘结构。绝缘结构是通过其限定的开口。第一层图案形成在开口的侧壁和底部上。在第一层图案上形成第二层图案并且基本上填充开口。

10. 发明授权

US08507353B2 Method of forming semiconductor device having self-aligned plug 有权
标题翻译：形成具有自对准插头的半导体器件的方法
公开(公告)号：US08507353B2
公开(公告)日：2013-08-13
申请号：US13188981
申请日：2011-07-22
申请人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L21/20 , H01L21/8244
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译：形成基板上的导电图案。形成具有露出导电图案的开口的绝缘层。底部电极形成在导电图案和开口的第一侧壁上。在底部电极和开口的第二侧壁上形成间隔物。间隔件和底部电极形成为低于绝缘层的顶表面。数据存储插头形成在底部电极和间隔件上。数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。在数据存储插头上形成位线。

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