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1. 发明授权

US07684970B2 Graphical user interface for use during processor simulation 失效
标题翻译：在处理器模拟期间使用的图形用户界面
公开(公告)号：US07684970B2
公开(公告)日：2010-03-23
申请号：US10877922
申请日：2004-06-25
申请人： Donald F. Hooper , Eric Walker , Dennis Rivard , Mark B. Rosenbluth
发明人： Donald F. Hooper , Eric Walker , Dennis Rivard , Mark B. Rosenbluth
IPC分类号： G06F9/44 , G06F3/00
CPC分类号： G06F11/3664 , G06F11/3636
摘要： In accordance with one exemplary embodiment, the present disclosure includes a method for executing application software during a simulation that models a processor for which the application software was developed. The method may include capturing results of the simulation to produce a simulation history. The method may also include providing a graphical user interface (GUI) that includes one or more cross-linked packet-centric views of the simulation history for packets operated on by the application software during the simulation. The cross-linked packet-centric views may include a packet status list GUI, a packet event list GUI, a packet dataflow GUI, a thread list GUI, and a thread history GUI. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：根据一个示例性实施例，本公开包括一种用于在仿真期间执行应用软件的方法，其对开发应用软件的处理器进行建模。该方法可以包括捕获模拟的结果以产生模拟历史。该方法还可以包括提供图形用户界面（GUI），其包括在模拟期间由应用软件操作的分组的模拟历史的一个或多个以交叉分组为中心的视图。以交叉分组为中心的视图可以包括分组状态列表GUI，分组事件列表GUI，分组数据流GUI，线程列表GUI和线程历史GUI。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

2. 发明授权

US07443836B2 Processing a data packet 有权
标题翻译：处理数据包
公开(公告)号：US07443836B2
公开(公告)日：2008-10-28
申请号：US10463217
申请日：2003-06-16
申请人： Donald F. Hooper , Mark B. Rosenbluth , Gilbert Wolrich , Matthew J. Adiletta , Hugh M. Wilkinson, III , Robert J. Kushlis
发明人： Donald F. Hooper , Mark B. Rosenbluth , Gilbert Wolrich , Matthew J. Adiletta , Hugh M. Wilkinson, III , Robert J. Kushlis
IPC分类号： H04L12/66
CPC分类号： G06F9/3851 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9057 , H04L49/9094
摘要： A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the execution threads.
摘要翻译：描述用于在设备处理数据分组的设备和方法。设备接收数据分组并且确定多个执行线程的一个或多个本地存储器中的可用存储器。该设备将分组信息存储在执行线程的本地存储器中的可用的一个中。

3. 发明授权

US07158964B2 Queue management 失效
标题翻译：队列管理
公开(公告)号：US07158964B2
公开(公告)日：2007-01-02
申请号：US10020815
申请日：2001-12-12
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Donald F. Hooper
IPC分类号： G06F17/30
CPC分类号： H04L49/9015 , Y10S707/99933
摘要： A method of managing queue entries includes storing addresses in a first queue entry as a linked list, each of the stored addresses including a cell count, retrieving a first address from the first queue entry, and modifying the linked list of addresses of the first queue entry based on the cell count of the first address retrieved.
摘要翻译：管理队列条目的方法包括将第一队列条目中的地址存储为链接列表，每个存储的地址包括小区计数，从第一队列条目检索第一地址，以及修改第一队列的链接的地址列表基于检索到的第一个地址的单元格计数输入。

4. 发明申请

US20130132683A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130132683A1
公开(公告)日：2013-05-23
申请号：US13713614
申请日：2012-12-13
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

5. 发明申请

US20120215984A1 HETEROGENEOUS PROCESSORS SHARING A COMMON CACHE 有权
标题翻译：共享缓存的异构处理器
公开(公告)号：US20120215984A1
公开(公告)日：2012-08-23
申请号：US13405798
申请日：2012-02-27
申请人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
发明人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0893 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F15/781 , G06F15/7842 , G06F15/7846 , G06F2212/283 , G06F2212/302 , G06F2212/314 , G06F2212/621
摘要： A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
摘要翻译：提出了一种提供异构处理器内核和共享缓存的多核处理器。

6. 发明授权

US08156285B2 Heterogeneous processors sharing a common cache 有权
标题翻译：共享共享缓存的异构处理器
公开(公告)号：US08156285B2
公开(公告)日：2012-04-10
申请号：US12459683
申请日：2009-07-06
申请人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
发明人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0893 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F15/781 , G06F15/7842 , G06F15/7846 , G06F2212/283 , G06F2212/302 , G06F2212/314 , G06F2212/621
摘要： A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
摘要翻译：提出了一种提供异构处理器内核和共享缓存的多核处理器。

7. 发明授权

US07707266B2 Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit 失效
标题翻译：可扩展的，高性能的全球互连方案，用于多线程，多处理系统级芯片网络处理器单元
公开(公告)号：US07707266B2
公开(公告)日：2010-04-27
申请号：US10997624
申请日：2004-11-23
申请人： Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Matthew Adiletta , Jeen-Xuan Miin , Bijoy Bose
发明人： Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Matthew Adiletta , Jeen-Xuan Miin , Bijoy Bose
IPC分类号： G06F13/00 , G06F15/173 , G06F15/16
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.
摘要翻译：用于多线程，多处理片上系统处理器单元的可扩展的高性能互连方案。实现该技术的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。在一个实施例中，机箱互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线路，用于目标的拉动数据总线写入和用于目标读取的推送数据总线。采用用于每个命令总线，拉数据总线和推数据总线的多路复用器电路来选择性地将给定集群连接到给定目标，以使命令和数据能够在给定集群和给定目标之间传递。

8. 发明申请

US20100011167A1 Heterogeneous processors sharing a common cache 有权
标题翻译：共享共享缓存的异构处理器
公开(公告)号：US20100011167A1
公开(公告)日：2010-01-14
申请号：US12459683
申请日：2009-07-06
申请人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
发明人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0893 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F15/781 , G06F15/7842 , G06F15/7846 , G06F2212/283 , G06F2212/302 , G06F2212/314 , G06F2212/621
摘要： A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
摘要翻译：提出了一种提供异构处理器内核和共享缓存的多核处理器。

9. 发明授权

US07610451B2 Data transfer mechanism using unidirectional pull bus and push bus 有权
标题翻译：数据传输机制采用单向拉总线和推送总线
公开(公告)号：US07610451B2
公开(公告)日：2009-10-27
申请号：US10057738
申请日：2002-01-25
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta
IPC分类号： G06F12/00 , G06F15/00
CPC分类号： G06F9/3824 , G06F9/3851
摘要： A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory resource for pushing the data to the processing agent via a push bus having a plurality of sources that arbitrate use of the push bus, and designating the memory resource for receiving the data from the processing agent via a pull bus having a plurality of destinations that arbitrate use of the pull bus.
摘要翻译：一种用于在编程代理和存储器资源之间传送数据的方法。该方法包括在处理代理和存储器资源之间传送数据，指定存储器资源，用于经由具有仲裁使用推送总线的多个源的推送总线将数据推送到处理代理，以及指定用于接收的存储器资源来自处理代理的数据经由具有仲裁使用拉总线的多个目的地的拉总线。

10. 发明申请

US20090119671A1 REGISTERS FOR DATA TRANSFERS 审中-公开
标题翻译：数据传输寄存器
公开(公告)号：US20090119671A1
公开(公告)日：2009-05-07
申请号：US12249786
申请日：2008-10-10
申请人： GILBERT WOLRICH , Mark B. Rosenbluth , Debra Bernstein , Matthew Adiletta , Hugh M. Wilkinson, III
发明人： GILBERT WOLRICH , Mark B. Rosenbluth , Debra Bernstein , Matthew Adiletta , Hugh M. Wilkinson, III
IPC分类号： G06F9/46 , G06F9/44 , G06F15/00 , G06F9/30 , G06F12/00
CPC分类号： G06F9/4843 , G06F9/30101 , G06F9/3012 , G06F9/30123 , G06F9/3851
摘要： A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.
摘要翻译：一种用于在多个硬件上下文和编程引擎中采用用于数据传输的寄存器以便于高性能数据处理的系统和方法。该系统和方法包括处理器，其包括具有寄存器的编程引擎，用于将驻留在执行编程引擎中的寄存器中的一个寄存器中的数据传送到驻留在相邻编程引擎中的后续寄存器中的寄存器。

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