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1. 发明授权

US06828210B2 Method of forming a device isolation trench in an integrated circuit device 有权
标题翻译：在集成电路器件中形成器件隔离沟槽的方法
公开(公告)号：US06828210B2
公开(公告)日：2004-12-07
申请号：US10080884
申请日：2002-02-22
申请人： Do-Hyung Kim , Sung-Bong Kim , Jung-In Hong
发明人： Do-Hyung Kim , Sung-Bong Kim , Jung-In Hong
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A method of forming a trench isolation in a semiconductor substrate is described, which comprises the steps of forming a trench on the substrate, forming a diffusion barrier insulating layer, forming a thermal oxide layer both sidewall and bottom of the trench contacted with the diffusion barrier insulating layer, forming a nitride liner, and forming trench isolation material to fill the trench. A multi-structure of the barrier layer and the thermal oxide layer is provided between the nitride liner and the trench, resulting in minimization of transistor characteristic deterioration. A thin thermal oxide layer is formed to achieve improved trench etching profile.
摘要翻译：描述了在半导体衬底中形成沟槽隔离的方法，其包括以下步骤：在衬底上形成沟槽，形成扩散阻挡绝缘层，形成与扩散阻挡层接触的沟槽的侧壁和底部的热氧化物层绝缘层，形成氮化物衬垫，以及形成沟槽隔离材料以填充沟槽。在氮化物衬垫和沟槽之间设置阻挡层和热氧化物层的多结构，导致晶体管特性劣化的最小化。形成薄的热氧化物层以实现改进的沟槽蚀刻轮廓。

2. 发明申请

US20050208725A1 Semiconductor device having shared contact and fabrication method thereof 有权
公开(公告)号：US20050208725A1
公开(公告)日：2005-09-22
申请号：US11143194
申请日：2005-06-01
申请人： Do-Hyung Kim , Jung-In Hong
发明人： Do-Hyung Kim , Jung-In Hong
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8234 , H01L21/3205 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/823425 , H01L21/76895 , H01L21/823475 , Y10S257/90 , Y10S257/903
摘要： Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

3. 发明授权

US07064026B2 Semiconductor device having shared contact and fabrication method thereof 有权
公开(公告)号：US07064026B2
公开(公告)日：2006-06-20
申请号：US11143194
申请日：2005-06-01
申请人： Do-Hyung Kim , Jung-In Hong
发明人： Do-Hyung Kim , Jung-In Hong
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/76895 , H01L21/823475 , Y10S257/90 , Y10S257/903
摘要： Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

4. 发明授权

US06927461B2 Semiconductor device having shared contact and fabrication method thereof 有权
标题翻译：具有共享接触的半导体器件及其制造方法
公开(公告)号：US06927461B2
公开(公告)日：2005-08-09
申请号：US10112413
申请日：2002-03-29
申请人： Do-Hyung Kim , Jung-In Hong
发明人： Do-Hyung Kim , Jung-In Hong
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8234 , H01L26/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823425 , H01L21/76895 , H01L21/823475 , Y10S257/90 , Y10S257/903
摘要： Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.
摘要翻译：半导体器件和制造方法。一种器件包括半导体衬底，通过栅极绝缘层与半导体衬底绝缘的栅电极，形成在栅电极两侧的LDD型源/漏区，形成在栅电极和衬底上的层间绝缘层，以及共享接触件，穿透所述层间绝缘层，并且使所述栅极电极和包括至少一部分轻掺杂漏极区域的LDD型源极/漏极区域中的一个接触。在栅极结构的两侧形成多层间隔物，并在形成LDD型区域中用作掩模。在接触开口中移除至少一层间隔件以加宽开口以接收接触塞。

5. 发明授权

US06653238B2 Method for forming semiconductor device having high-density contacts 有权
公开(公告)号：US06653238B2
公开(公告)日：2003-11-25
申请号：US10062775
申请日：2002-01-30
申请人： Sung-Bong Kim , Jung-In Hong , Do-Hyung Kim
发明人： Sung-Bong Kim , Jung-In Hong , Do-Hyung Kim
IPC分类号： H01L21311
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76813
摘要： Methods of forming high-density contacts are provided. An interlayer insulating layer and an auxiliary layer having interconnection line patterns are sequentially formed on a substrate in which a conductive region is formed. Next, a contact photoresist pattern having a bar-shaped pattern is formed on the auxiliary layer. The bar-shaped pattern is substantially orthogonal to the interconnection line pattern formed in the auxiliary layer. Then, the interlayer insulating layer is etched at a contact region using the contact photoresist pattern and the auxiliary layer having the interconnection line pattern therein as an etching mask. Subsequently, the interlayer insulating layer is etched using the auxiliary layer having the interconnection line pattern as an etching mask to form a contact hole that extends through the interlayer insulating layer to the conductive region and to form an interconnection groove in an upper portion of the interlayer insulating layer.

6. 发明授权

US5089436A Method for fabricating a semiconductor device by slope etching a polysiliow layer 失效
标题翻译：通过斜面蚀刻多层薄膜来制造半导体器件的方法
公开(公告)号：US5089436A
公开(公告)日：1992-02-18
申请号：US519261
申请日：1990-05-02
申请人： Jung-In Hong , Byung-Deok Yoo , Tae-Hyuk Ahn
发明人： Jung-In Hong , Byung-Deok Yoo , Tae-Hyuk Ahn
IPC分类号： H01L23/52 , H01L21/285 , H01L21/306 , H01L21/3205 , H01L21/3213 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L21/28525 , H01L21/32137 , Y10S438/924 , Y10S438/978
摘要： This invention provides a method for manufacturing a semiconductor device which prevents residues from remaining around an etching pattern of a poly-silicon by making the poly-silicon be gradiently etched out. An oxide barrier layer is deposited over a poly-silicon layer, and impurities are implanted through the oxide barrier layer, wherein the concentration difference of impurities makes the poly-silicon have a graded sidewalls, and the value of resistance is controlled by the quantity of impurities. After removing the oxide barrier layer the poly-silicon is selectively etched into a poly electrode having a graded sidewall. The thermal treatment of the poly electrode is carried out and a polysilicon for another electrode is deposited and etched out.
摘要翻译：本发明提供一种制造半导体器件的方法，该方法通过使多晶硅被梯度蚀刻出来，防止残留物残留在多晶硅的蚀刻图案周围。在多晶硅层上沉积氧化物阻挡层，并且通过氧化物阻挡层注入杂质，其中杂质的浓度差使得多晶硅具有渐变侧壁，并且电阻值由杂质。在去除氧化物阻挡层之后，将多晶硅选择性地蚀刻到具有渐变侧壁的多晶电极中。进行聚电极的热处理，并沉积并腐蚀出另一电极的多晶硅。

7. 发明授权

US5395795A Method for fabricating a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5395795A
公开(公告)日：1995-03-07
申请号：US80053
申请日：1993-06-22
申请人： Jung-In Hong , Je-Sung Hwang , Min-Suk Han
发明人： Jung-In Hong , Je-Sung Hwang , Min-Suk Han
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/441
CPC分类号： H01L21/76843 , H01L21/76855
摘要： A process for forming a barrier metal layer and a metal layer on the surface of a contact hole formed on a semiconductor substrate. A titanium and a first titanium nitride layers are sequentially deposited on the surface of the contact hole and annealed, and thereafter, a second titanium nitride layer is deposited on the first titanium nitride layer and annealed, to thereby form a barrier metal layer. A first aluminum layer alloyed with silicon and copper of a given quantity, and a second aluminum layer alloyed with copper of a given quantity, are sequentially deposited on the barrier metal layer, and thereafter performed, the annealing process is performed. A third aluminum layer alloyed with copper of a given quantity is deposited on the second aluminum layer and annealed, to thereby form a metal layer. Accordingly, a leakage current is considerably reduced due to preventions of a silicon extraction phenomenon and an aluminum spike phenomenon, and a contact resistance is reduced and a step coverage is improved by effectively burying the contact hole through the above process, to thereby obtain a reliable semiconductor device.
摘要翻译：在半导体基板上形成的接触孔的表面上形成阻挡金属层和金属层的工序。将钛和第一氮化钛层依次沉积在接触孔的表面上并退火，然后在第一氮化钛层上沉积第二氮化钛层并进行退火，从而形成阻挡金属层。将与给定量的硅和铜合金的第一铝层和与给定量的铜合金化的第二铝层依次沉积在阻挡金属层上，然后进行退火处理。将与给定量的铜合金化的第三铝层沉积在第二铝层上并退火，从而形成金属层。因此，由于硅提取现象和铝尖峰现象的防止，泄漏电流显着降低，并且通过上述过程有效地埋入接触孔，降低了接触电阻并提高了台阶覆盖率，从而获得可靠的半导体器件。

8. 发明授权

US5252177A Method for forming a multilayer wiring of a semiconductor device 失效
标题翻译：用于形成半导体器件的多层布线的方法
公开(公告)号：US5252177A
公开(公告)日：1993-10-12
申请号：US736772
申请日：1991-07-29
申请人： Jong-Seo Hong , Jin-Hong Kim , Jung-In Hong
发明人： Jong-Seo Hong , Jin-Hong Kim , Jung-In Hong
IPC分类号： H01L21/30 , H01L21/027 , H01L21/304 , H01L21/3205 , H01L21/768 , H01L23/52 , B44C1/22 , C23F7/00
CPC分类号： H01L21/76838 , H01L21/76802 , H01L21/76877
摘要： A method for forming a multilayer wiring, in a method for manufacturing a semiconductor device, is disclosed. The method comprises: forming a contact hole 33 on the surface of a conductive layer 29 by a photolithography, removing a photoresist by using plasma ashing at a predetermined temperature, pressure and amount of oxygen per unit cubic, and simultaneously forming a protective layer 35 consisting of a oxide layer on the surface of the exposed conductive layer. Thus, damage of the surface of wiring caused by the chemical reaction of an organic solvent and water in the subsequent process thereof, is prevented, to provide high density and high speed semiconductor integrated circuit whose electrode characteristics between two wiring layers is improved.
摘要翻译：公开了一种用于形成多层布线的方法，在半导体器件的制造方法中。该方法包括：通过光刻在导电层29的表面上形成接触孔33，通过在预定温度下使用等离子体灰化，压力和每单位立方体的氧量来除去光致抗蚀剂，同时形成保护层35，其包括的暴露的导电层的表面上的氧化物层。因此，防止了在其后续过程中由有机溶剂和水的化学反应引起的布线表面的损伤，从而提供了其两个布线层之间的电极特性提高的高密度和高速的半导体集成电路。

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