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1. 发明授权

US08630198B1 Apparatus and methods of dynamic transmit equalization 有权
标题翻译：动态传输均衡的装置和方法
公开(公告)号：US08630198B1
公开(公告)日：2014-01-14
申请号：US12983180
申请日：2010-12-31
申请人： Divya Vijayaraghavan , Gopi Krishnamurthy , Ning Xue , Chong H. Lee
发明人： Divya Vijayaraghavan , Gopi Krishnamurthy , Ning Xue , Chong H. Lee
IPC分类号： G01R31/08
CPC分类号： H04L25/03885 , H04B3/04 , H04B3/32 , H04L25/03343
摘要： One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry. Other embodiments, aspects, and features are also disclosed.
摘要翻译：一个实施例涉及被配置为执行双向通道的动态发送均衡的集成电路。该集成电路包括物理编码和媒体访问控制电路之间的接口，以及在物理编码电路外部的配置成使用所述接口执行动态发送均衡的均衡控制电路。另一个实施例涉及一种包括物理编码电路和媒体访问控制电路的收发器电路。收发器电路还包括物理编码电路和媒体访问控制电路之间的接口以及在物理编码电路之外的均衡控制器，并且被配置为使用所述接口执行动态发送均衡。接口被配置为以时间复用的信号格式提供从媒体访问控制电路到物理编码电路的传输系数数据。还公开了其它实施例，方面和特征。

2. 发明授权

US08458383B1 Flexible interface for stacked protocol in a programmable integrated circuit device 有权
标题翻译：可编程集成电路器件中堆叠协议的灵活接口
公开(公告)号：US08458383B1
公开(公告)日：2013-06-04
申请号：US11848016
申请日：2007-08-30
申请人： Curt Wortman , Chong H. Lee , Divya Vijayaraghavan , Ning Xue
发明人： Curt Wortman , Chong H. Lee , Divya Vijayaraghavan , Ning Xue
IPC分类号： G06F13/14 , G06F15/16
CPC分类号： G06F13/4059 , Y02D10/14 , Y02D10/151
摘要： On programmable device, each layer of a programmable interface, for a protocol which has a protocol stack including at least a physical layer, a data link layer and a transaction layer, is selectably bypassable. When a layer is bypassed, all other layers downstream of that layer also are bypassed. In addition, the interface may be divided into different clock domains running at different clock rates, reflecting clock rates within the programmable device and outside the programmable device. Layers may be bypassed to allow a user to substitute a custom layer in programmable logic, or to substitute an updated layer for debugging purposes.
摘要翻译：在可编程设备上，用于具有包括至少物理层，数据链路层和事务层的协议栈的协议的可编程接口的每层可选择地旁路。当旁路一层时，该层下游的所有其他层也被旁路。此外，该接口可以被划分为以不同的时钟速率运行的不同的时钟域，反映了可编程器件内部和可编程器件外部的时钟速率。可以绕过图层以允许用户替换可编程逻辑中的自定义层，或者替换更新的层进行调试。

3. 发明授权

US07627806B1 Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device 有权
标题翻译：用于可编程逻辑器件中的物理编码子层的集成硬连线或部分硬连线CRC生成和/或检查架构
公开(公告)号：US07627806B1
公开(公告)日：2009-12-01
申请号：US11436463
申请日：2006-05-17
申请人： Divya Vijayaraghavan , Michael Menghui Zheng , Chong H. Lee , Ning Xue , Tam Nguyen
发明人： Divya Vijayaraghavan , Michael Menghui Zheng , Chong H. Lee , Ning Xue , Tam Nguyen
IPC分类号： H03M13/09
CPC分类号： H04L1/0052 , H03M13/09 , H03M13/6516 , H04L1/0061
摘要： A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).
摘要翻译：可编程逻辑集成电路器件（“PLD”）包括至少部分硬接线以执行HSSI操作的至少一些功能方面的高速串行接口（“HSSI”）电路。循环冗余校验（CRC）生成和/或检查电路现在包括在该HSSI电路中，并且再次，该CRC电路至少部分地硬接线以执行其操作的至少一些功能方面。

4. 发明授权

US08188774B1 Apparatus and methods for activation of an interface on an integrated circuit 有权
标题翻译：用于激活集成电路上的接口的装置和方法
公开(公告)号：US08188774B1
公开(公告)日：2012-05-29
申请号：US12833718
申请日：2010-07-09
申请人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
发明人： Gopi Krishnamurthy , Binh Ton , Ning Xue , Tim Tri Hoang , Michael Menghui Zheng , Weiqi Ding
IPC分类号： H03L7/00
CPC分类号： H03K19/1774
摘要： One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.
摘要翻译：一个实施例涉及在集成电路的核心变得可操作时激活集成电路上的接口的方法。收发器通道的偏移校准由物理介质连接电路执行。传输频率被收发器通道的发射机锁相环锁定，并且接收频率被收发信机的接收机锁相环锁定。随后，当集成电路的核心部件变得可操作时，该接口被激活。另一实施例涉及包括收发信道电路，接口处理器和复位控制状态机的集成电路。另一实施例涉及包括复位控制状态机，收发信道电路，信道输入转向多路复用器和信道输出转向多路复用器的控制电路。还公开了其它实施例，方面和特征。

5. 发明授权

US07386767B1 Programmable bit error rate monitor for serial interface 有权
标题翻译：串行接口的可编程误码率监视器
公开(公告)号：US07386767B1
公开(公告)日：2008-06-10
申请号：US10958447
申请日：2004-10-05
申请人： Ning Xue , Chong H Lee
发明人： Ning Xue , Chong H Lee
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/076
摘要： A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.
摘要翻译：可编程误码率监视器包括错误计数器，具有可编程上限的监视周期计数器以设置监视周期，以及将实际错误计数与可编程阈值进行比较的错误标志发生器。错误标志生成器可以生成不同灵敏度级别的标志，并且用户可以可编程地选择这些标志之一。这三个标志可以由独立的比较器产生，或者它们可以从基本错误标志中外推，例如通过仅将错误计数的某些位与阈值的相应位进行比较。

6. 发明授权

US07199732B1 Data converter with reduced component count for padded-protocol interface 有权
标题翻译：数据转换器，减少了填充协议接口的组件数量
公开(公告)号：US07199732B1
公开(公告)日：2007-04-03
申请号：US11139083
申请日：2005-05-26
申请人： Ning Xue , Chong H Lee
发明人： Ning Xue , Chong H Lee
IPC分类号： H03M7/00
CPC分类号： H04L25/4908
摘要： A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).
摘要翻译：用于填充协议接口的数据转换器或“变速箱”通过处理较窄的中间数据流来减少数量的组件，同时将其中间输入和输出的时钟速度乘以使其处理更多的数据时钟周期。数据流可以缩小为原始宽度（原始宽度除外）的任何整数因子。

7. 发明授权

US08363770B1 Oversampling with programmable pointer adjustment 有权
标题翻译：可编程指针调整过采样
公开(公告)号：US08363770B1
公开(公告)日：2013-01-29
申请号：US11555570
申请日：2006-11-01
申请人： Ning Xue , Chong H. Lee
发明人： Ning Xue , Chong H. Lee
IPC分类号： H04L12/50
CPC分类号： H04L7/0338 , H04L7/0331
摘要： Systems, methods, and circuits extract data from an oversampled data stream in the presence of noise and/or jitter. Pointers decide which data samples of the oversampled data stream are extracted. Some of the pointers occurring right after a data transition are positioned based on the location of previous pointers, rather than using the data transition points as occurs during an alignment. Settings such as the frequency of how often a pointer is aligned with a data transition and a maximum adjustment amount during an alignment may be programmable.
摘要翻译：系统，方法和电路在存在噪声和/或抖动的情况下从过采样数据流中提取数据。指针决定提取过采样数据流的哪些数据样本。在数据转换之后发生的一些指针基于先前指针的位置而定位，而不是使用在对齐期间发生的数据转换点。诸如指针与数据转换对齐频率的频率以及在对准期间的最大调整量的设置可以是可编程的。

8. 发明授权

US07259699B1 Circuitry for providing configurable running disparity enforcement in 8B/10B encoding and error detection 有权
标题翻译：用于在8B / 10B编码和错误检测中提供可配置的运行视差执行的电路
公开(公告)号：US07259699B1
公开(公告)日：2007-08-21
申请号：US11285944
申请日：2005-11-23
申请人： Ning Xue , Chong H Lee
发明人： Ning Xue , Chong H Lee
IPC分类号： H03M7/00
CPC分类号： H03M5/145
摘要： An integrated circuit like a programmable logic device (“PLD”) includes a communication channel employing 8B/10B coding. Disparity information determined by 8B/10B decoder circuitry in the communication channel is supplied to other circuitry of the PLD so that any requirement for disparity to have a particular value in conjunction with certain received codes can be checked. On the transmitter side, circuitry is provided for selectively forcing the 8B/10B encoder to use a commanded disparity (which can be either positive or negative) under particular circumstances.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路包括采用8B / 10B编码的通信信道。在通信信道中由8B / 10B解码器电路确定的视差信息被提供给PLD的其他电路，使得可以检查与特定接收码相结合具有特定值的差异的任何要求。在发射机侧，提供电路用于在特定情况下选择性地强制8B / 10B编码器使用命令的差异（其可以是正的或负的）。

9. 发明授权

US07162553B1 Correlating high-speed serial interface data and FIFO status signals in programmable logic devices 有权
标题翻译：在可编程逻辑器件中关联高速串行接口数据和FIFO状态信号
公开(公告)号：US07162553B1
公开(公告)日：2007-01-09
申请号：US10956684
申请日：2004-10-01
申请人： Ning Xue , Chong H Lee
发明人： Ning Xue , Chong H Lee
IPC分类号： G06F13/12 , H03K19/0175
CPC分类号： H03G1/0088 , H03G1/0094
摘要： Status signals that are generated by one or more FIFO buffers in a high-speed serial interface (“HSSI”) may be combined with transmitted data samples in order to correlate the status signals to the respective data samples. The combined data and status signals may be transmitted either to the subsequent stages of the HSSI datapath or directly to the PLD via a dedicated path with less latency. The combined data and status signals can be used to determine whether a data sample corresponds to a valid data sample or an idle sequence, thereby allowing a user to control the flow of data.
摘要翻译：由高速串行接口（“HSSI”）中的一个或多个FIFO缓冲器生成的状态信号可以与发送的数据样本组合，以便将状态信号与各个数据样本相关联。组合的数据和状态信号可以被发送到HSSI数据路径的后续阶段，或者通过具有较小延迟的专用路径直接发送到PLD。组合的数据和状态信号可用于确定数据样本是否对应于有效数据样本或空闲序列，从而允许用户控制数据流。

10. 发明授权

US07064685B1 Data converter with reduced component count for padded-protocol interface 失效
标题翻译：数据转换器，减少了填充协议接口的组件数量
公开(公告)号：US07064685B1
公开(公告)日：2006-06-20
申请号：US10969448
申请日：2004-10-20
申请人： Ning Xue , Chong H. Lee
发明人： Ning Xue , Chong H. Lee
IPC分类号： H03M7/00
CPC分类号： H04L25/4908
摘要： A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).
摘要翻译：用于填充协议接口的数据转换器或“变速箱”通过处理较窄的中间数据流来减少数量的组件，同时将其中间输入和输出的时钟速度乘以使其处理更多的数据时钟周期。数据流可以缩小为原始宽度（原始宽度除外）的任何整数因子。

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