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1. 发明授权

US5112762A High angle implant around top of trench to reduce gated diode leakage 失效
标题翻译：在沟槽顶部的高角度植入物，以减少栅极二极管泄漏
公开(公告)号：US5112762A
公开(公告)日：1992-05-12
申请号：US622468
申请日：1990-12-05
申请人： Dirk N. Anderson , William R. McKee , Gishi Chung
发明人： Dirk N. Anderson , William R. McKee , Gishi Chung
IPC分类号： H01L21/265 , H01L21/316 , H01L21/32 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L29/66181 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/26586 , H01L21/31662 , H01L21/32
摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.
摘要翻译：公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。电容器的存储节点通过将诸如注入的砷的存储节点材料以第一倾斜和第二倾斜放置在器件的沟槽壁中而形成。第二倾斜的角度优选地比第一倾斜的角度更大，更高。这种较高的角度为存储节点提供了围绕沟槽壁上部的更大的掺杂浓度。这种较大的掺杂浓度降低了从存储节点的上部泄漏到半导体材料的衬底中的电荷。还公开了一种用于动态随机存取存储器件的沟槽型存储电容器。

2. 发明授权

US06861348B2 Pre-pattern surface modification of low-k dielectrics 有权
标题翻译：低k电介质的预图形表面改性
公开(公告)号：US06861348B2
公开(公告)日：2005-03-01
申请号：US09982654
申请日：2001-10-18
申请人： Brian K. Kirkpatrick , Michael Morrison , Andrew J. McKerrow , Kenneth J. Newton , Dirk N. Anderson
发明人： Brian K. Kirkpatrick , Michael Morrison , Andrew J. McKerrow , Kenneth J. Newton , Dirk N. Anderson
IPC分类号： H01L21/288 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76835 , H01L21/2885 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76808 , H01L21/76826
摘要： A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The D-W or D-W-D treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).
摘要翻译：低k介电层（104）用干湿（DW）或干 - 湿 - 干（DWD）工艺处理以改善图案抗蚀剂中毒由于低k膜（104）之间的相互作用而发生，例如 OSG和DUV抗蚀剂（130）。执行D-W或D-W-D处理以在形成图案（130）之前或在图案（130）的返工期间预处理低k电介质（104）。

3. 发明授权

US06559050B1 Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices 有权
标题翻译：制造亚微米级CMOS器件的高热稳定接触形成工艺
公开(公告)号：US06559050B1
公开(公告)日：2003-05-06
申请号：US09691907
申请日：2000-10-19
申请人： William R. McKee , Jiong-Ping Lu , Ming-Jang Hwang , Dirk N. Anderson , Wei Lee
发明人： William R. McKee , Jiong-Ping Lu , Ming-Jang Hwang , Dirk N. Anderson , Wei Lee
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76855 , H01L21/76856 , H01L21/76867
摘要： A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSiYNZ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via. According to another embodiment, a silicon surface layer is applied to the exposed surface of the dielectric layer and to the exposed surface of the substrate prior to formation of the nitrided surface layer. A layer of tungsten, tungsten/tungsten nitride, or tungsten nitride is formed to fill the via. After annealing, a tungsten conducting plug is formed with a tungsten-silicon-nitride interface region with the substrate.
摘要翻译：与集成电路一起使用的导电插头/接触结构包括形成在通孔中的钨导电插塞，其中钨硅氮化物（WSiYNZ）区域提供钨导电插塞和衬底（硅）层之间的界面。在形成填充通孔的钨/氮化钨层之前，形成界面区域，在暴露的电介质表面和暴露的衬底表面上（即，通过电介质层中的通孔暴露）提供氮化表面层。该结构退火形成导电插塞和基板之间的钨 - 氮化硅界面的钨导电塞。根据另一个实施例，在形成钨层以填充通孔之前，氮化表面层上形成氮化钨表面层。根据另一实施例，在形成氮化表面层之前，将硅表面层施加到介电层的暴露表面和衬底的暴露表面。形成一层钨，钨/氮化钨或氮化钨以填充通孔。在退火之后，形成具有与基板的钨 - 氮化硅界面区域的钨导电塞。

4. 发明授权

US5796151A Semiconductor stack having a dielectric sidewall for prevention of oxidation of tungsten in tungsten capped poly-silicon gate electrodes 失效
标题翻译：具有用于防止钨封端的多晶硅栅电极中钨的氧化的电介质侧壁的半导体叠层
公开(公告)号：US5796151A
公开(公告)日：1998-08-18
申请号：US770019
申请日：1996-12-19
申请人： Wei-Yung Hsu , Dirk N. Anderson , Robert Kraft
发明人： Wei-Yung Hsu , Dirk N. Anderson , Robert Kraft
IPC分类号： H01L29/78 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/76 , H01L23/58 , H01L29/94 , H01L31/62
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28114 , H01L21/28167 , H01L21/28512 , H01L29/4941 , H01L29/66575
摘要： In an integrated circuit, gate electrode stack of which is subjected to self-alignment processes, the sheet resistance is lowered by including a tungsten layer 15. The tungsten layer 14 is protected by a sidewall material 21 of SiN.sub.x or SiO.sub.2 after an etching step which did not extend to the substrate 11. During a subsequent etching step in which the stack extends to the substrate 11, the sidewall material 31 acts as a hard mask protecting the upper portion of the stack. After the lower portion of the stack is protected by a re-oxidation layer 41, the entire stack can be processed further without deterioration of the sheet resistance of the tungsten layer 15.
摘要翻译：在其栅极电极堆叠进行自对准处理的集成电路中，通过包括钨层15来降低薄层电阻。在蚀刻步骤之后，钨层14被SiN x或SiO 2的侧壁材料21保护，没有延伸到基板11.在其中堆叠延伸到基板11的随后的蚀刻步骤中，侧壁材料31用作保护堆叠的上部的硬掩模。在堆叠的下部被再氧化层41保护之后，可以进一步处理整个堆叠而不会降低钨层15的薄层电阻。

5. 发明授权

US06373088B1 Edge stress reduction by noncoincident layers 失效
公开(公告)号：US06373088B1
公开(公告)日：2002-04-16
申请号：US09096012
申请日：1998-06-10
申请人： Siang Ping Kwok , William F. Richardson , Dirk N. Anderson
发明人： Siang Ping Kwok , William F. Richardson , Dirk N. Anderson
IPC分类号： H01L2100
摘要： The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

6. 发明授权

US5300447A Method of manufacturing a minimum scaled transistor 失效
标题翻译：制造最小比例晶体管的方法
公开(公告)号：US5300447A
公开(公告)日：1994-04-05
申请号：US953632
申请日：1992-09-29
申请人： Dirk N. Anderson
发明人： Dirk N. Anderson
IPC分类号： H01L29/41 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66621
摘要： An extremely small minimum scaled Metal-Oxide-Semiconductor, MOS, transistor is manufactured by forming a trench in a semiconductor substrate, forming a gate in the trench, and then forming source and drain regions. The source and drain regions may be diffused into the semiconductor substrate and annealed to drive the diffusions around the trench corners, thus forming the transistor channel. This improves punchthrough resistance of the transistor while yielding an extremely small gate channel. The diffusion concentration will be larger near the surface of the semiconductor substrate and smaller near the plane of the gate channel underneath the trench bottom. The trench corners have the effect of serving as a line source of dopant for diffusion under the trench such that the doping profile is the same along a radius of a cylindrical junction, thus keeping the minimum diffusion separation at the channel surface.
摘要翻译：通过在半导体衬底中形成沟槽，在沟槽中形成栅极，然后形成源极和漏极区域，制造极小的最小尺寸的金属氧化物半导体MOS晶体管。源极和漏极区域可以扩散到半导体衬底中并退火以驱动围绕沟槽角的扩散，从而形成晶体管沟道。这提高了晶体管的穿透阻抗，同时产生极小的栅极通道。在半导体衬底的表面附近的扩散浓度将更大，并且在沟槽底部下方的栅极通道的平面附近更小。沟槽角部具有用作沟槽下方扩散的掺杂剂的线源的作用，使得掺杂分布沿着圆柱形结的半径相同，从而保持在沟道表面处的最小扩散分离。

7. 发明授权

US4751198A Process for making contacts and interconnections using direct-reacted silicide 失效
标题翻译：使用直接反应的硅化物进行接触和互连的方法
公开(公告)号：US4751198A
公开(公告)日：1988-06-14
申请号：US774675
申请日：1985-09-11
申请人： Dirk N. Anderson
发明人： Dirk N. Anderson
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/283
CPC分类号： H01L21/76879 , H01L21/28518 , Y10S148/147
摘要： Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. A thin layer of titanium or the like is deposited, extending into a contact hole, then polysilicon is deposited over the titanium coating the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create a titanium silicide layer, including conductive sidewalls or a plug. Metal contacts and interconnections then engage the direct-reacted silicide rather than relying upon step coverage.
摘要翻译：用于半导体集成电路的金属触点和互连通过使用直接反应的硅化物来增加步骤或侧壁覆盖的工艺形成。沉积薄层的钛等，延伸到接触孔中，然后将多晶硅沉积在钛涂层上的台阶或孔的垂直侧面上。沉积第二薄钛层，然后热处理形成硅化物以产生包括导电侧壁或插头的硅化钛层。然后金属接触和互连接合直接反应的硅化物，而不是依赖于台阶覆盖。

8. 发明授权

US4744858A Integrated circuit metallization with reduced electromigration 失效
公开(公告)号：US4744858A
公开(公告)日：1988-05-17
申请号：US710346
申请日：1985-03-11
申请人： James M. McDavid , Dirk N. Anderson
发明人： James M. McDavid , Dirk N. Anderson
IPC分类号： H01L21/768 , H01L23/532 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76804 , H01L23/53214 , H01L2924/0002 , Y10S438/927 , Y10S438/964
摘要： The specification discloses a method and a device wherein circuit elements (10) are formed on the surface of a semiconductor body (12). A layer of oxide (22) is applied over the circuit element (10). An aperture (32) is opened through the oxide layer (22). The surface of oxide layer (22) is nonuniformly substantially roughened. A layer of metal (24) such as aluminum is formed over the oxide layer (22) and extends into the aperture (32) for contact with a portion of the device (10). The layer of metal (24) has increased granular structure and a roughened exterior surface to provide enhanced electromigration properties.

9. 发明授权

US06720247B2 Pre-pattern surface modification for low-k dielectrics using A H2 plasma 有权
标题翻译：使用A H2等离子体的低k电介质的预图案表面改性
公开(公告)号：US06720247B2
公开(公告)日：2004-04-13
申请号：US10001327
申请日：2001-10-25
申请人： Brian K. Kirkpatrick , Michael Morrison , Andrew J. McKerrow , Kenneth J. Newton , Dirk N. Anderson
发明人： Brian K. Kirkpatrick , Michael Morrison , Andrew J. McKerrow , Kenneth J. Newton , Dirk N. Anderson
IPC分类号： H01J214763
CPC分类号： H01L21/76835 , H01L21/31116 , H01L21/31138 , H01L21/76808 , H01L21/76826
摘要： A low-k dielectric layer (104) is treated with a dry H2 plasma pretreatment to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The H2 plasma pre-treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).
摘要翻译：用干H 2等离子体预处理来处理低k电介质层（104）以改善图案。由于低k膜（104）如OSG和DUV抗蚀剂（130）之间的相互作用，发生抗蚀剂中毒。执行H2等离子体预处理以在形成图案（130）之前或在图案（130）的返工期间预处理低k电介质（104）。

10. 发明授权

US06187656B1 CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes 有权
标题翻译：用于制造稳定的低电阻率多金属栅电极的基于CVD的工艺
公开(公告)号：US06187656B1
公开(公告)日：2001-02-13
申请号：US09167951
申请日：1998-10-07
申请人： Jiong Ping Lu , Ming Hwang , Dirk N. Anderson , Jorge A. Kittl , Hun-Lian Tsai
发明人： Jiong Ping Lu , Ming Hwang , Dirk N. Anderson , Jorge A. Kittl , Hun-Lian Tsai
IPC分类号： H01L213205
CPC分类号： H01L21/28202 , H01L21/28061 , H01L29/4916 , H01L29/518
摘要： A process for forming a W-poly gate stack (110) comprising the steps of: (1) deposition of doped polysilicon (112) on a thin dielectric layer (108) covered substrate (102), (2) deposition of WNx by a CVD-based process, (3) thermal treatment to covert WNx into thermally stable barrier, WSiNx, (114) and to remove excess nitrogen and (4) deposition of W layer (116). The stack layers are then etched to form the gate electrode (110).
摘要翻译：一种用于形成W-多晶硅堆叠（110）的工艺，包括以下步骤：（1）将掺杂多晶硅（112）沉积在覆盖有薄膜（108）的衬底（102）上，（2）WNx沉积基于CVD的工艺，（3）将WNx转变成热稳定势垒的热处理，WSiNx，（114）和去除多余的氮和（4）W层（116）的沉积。然后对叠层进行蚀刻以形成栅电极（110）。

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