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1. 发明授权

US07034653B2 Semiconductor resistor 有权
标题翻译：半导体电阻
公开(公告)号：US07034653B2
公开(公告)日：2006-04-25
申请号：US10768771
申请日：2004-01-30
申请人： Dipankar Bhattacharya , John Christopher Kriz , Stefan Allen Siegel , Joseph E. Simko , Yehuda Smooha
发明人： Dipankar Bhattacharya , John Christopher Kriz , Stefan Allen Siegel , Joseph E. Simko , Yehuda Smooha
IPC分类号： H01C1/01
CPC分类号： H01L28/20 , H01C1/14 , H01L23/5228 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor resistor comprises a resistor body formed on a semiconductor substrate and first and second conductive terminals electrically connected to the resistor body at opposite ends thereof. The semiconductor resistor further includes at least first and second conductive paths between at least one of the first and second conductive terminals and the resistor body. The at least one conductive terminal is configured such that a resistance of the at least one conductive terminal between the at least first and second conductive paths is substantially matched to a resistance of the resistor body between the at least first and second conductive paths. In this manner, a current distribution between the at least first and second conductive paths is substantially matched.
摘要翻译：半导体电阻器包括形成在半导体衬底上的电阻体和在其两端电连接到电阻体的第一和第二导电端子。半导体电阻器还包括在第一和第二导电端子和电阻器主体中的至少一个之间的至少第一和第二导电路径。至少一个导电端子被配置为使得至少第一和第二导电路径之间的至少一个导电端子的电阻基本上与至少第一和第二导电路径之间的电阻体的电阻相匹配。以这种方式，至少第一和第二导电路径之间的电流分布基本匹配。

2. 发明授权

US06774698B1 Voltage translator circuit for a mixed voltage circuit 失效
标题翻译：用于混合电压电路的电压转换器电路
公开(公告)号：US06774698B1
公开(公告)日：2004-08-10
申请号：US10354883
申请日：2003-01-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Christopher Kriz , Bernard Lee Morris , Stefan Allen Siegel
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Christopher Kriz , Bernard Lee Morris , Stefan Allen Siegel
IPC分类号： H03L500
CPC分类号： H03K3/356113 , H03K17/102
摘要： An apparatus is disclosed for translating a lower voltage signal, utilized in a low voltage integrated circuit, to a higher voltage signal suitable for use in a high voltage circuit. The apparatus includes a low voltage transistor assembly capable of operating in response to the lower voltage signal; a voltage regulator which is configured to limit an applied voltage across the low voltage transistor assembly; and a high voltage converter which is responsive to the operation of the low voltage transistor assembly to generate the higher voltage signal. The voltage regulator includes a reference voltage generator and a voltage limiter.
摘要翻译：公开了一种用于将低电压集成电路中使用的较低电压信号转换成适用于高压电路的较高电压信号的装置。该装置包括能够响应于较低电压信号而工作的低压晶体管组件; 配置为限制所述低压晶体管组件上的施加电压的电压调节器; 以及响应于低电压晶体管组件的操作以产生较高电压信号的高压转换器。电压调节器包括参考电压发生器和限压器。

3. 发明授权

US07218169B2 Reference compensation circuit 有权
标题翻译：参考补偿电路
公开(公告)号：US07218169B2
公开(公告)日：2007-05-15
申请号：US10744801
申请日：2003-12-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Christopher Kriz , Bernard Lee Morris , Jeffrey Jay Nagy , Stefan Allen Siegel
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Christopher Kriz , Bernard Lee Morris , Jeffrey Jay Nagy , Stefan Allen Siegel
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/245 , G05F3/247
摘要： A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.
摘要翻译：补偿电路包括参考电路，该参考电路包括参考NMOS器件和参考PMOS器件。参考电路可操作以产生第一参考信号和第二参考信号，第一参考信号是参考NMOS器件的处理特性，电压特性和温度特性中的至少一个的函数，第二参考信号信号是参考PMOS器件的工艺特性，电压特性和温度特性中的至少一个的函数。补偿电路还包括连接到参考电路的控制电路。控制电路可操作以接收第一和第二参考信号并产生一个或多个输出信号，用于补偿至少一个NMOS器件的工艺特性，电压特性和温度特性中的至少一个的变化，并且在响应于第一和第二参考信号，要补偿的电路中的至少一个PMOS器件可连接到控制电路。

4. 发明授权

US06992489B2 Multiple voltage level detection circuit 失效
标题翻译：多电压电平检测电路
公开(公告)号：US06992489B2
公开(公告)日：2006-01-31
申请号：US10776778
申请日：2004-02-11
申请人： Dipankar Bhattacharya , John Christopher Kriz , Joseph E. Simko
发明人： Dipankar Bhattacharya , John Christopher Kriz , Joseph E. Simko
IPC分类号： G01R19/26 , G01R19/257
CPC分类号： G01R19/16595 , G01R19/16519
摘要： A circuit configurable for indicating a voltage level of an input signal applied to the circuit includes at least one transistor having a first terminal connected to a first voltage supply, a second terminal configured for receiving the input signal, and a third terminal operatively coupled to an output of the circuit. The circuit further includes a passive load connected between the third terminal of the transistor and a second voltage supply. The circuit is configured to generate an output signal at the output of the circuit. The output signal being at a first value indicates that the input signal is substantially at a first voltage level, and the output signal being at a second value indicates that the input signal is substantially at a second voltage level.
摘要翻译：可配置为指示施加到电路的输入信号的电压电平的电路包括至少一个晶体管，其具有连接到第一电压源的第一端子，被配置为接收输入信号的第二端子，以及可操作地耦合到输出电路。电路还包括连接在晶体管的第三端子和第二电压源之间的无源负载。电路被配置为在电路的输出处产生输出信号。输出信号处于第一值表示输入信号基本上处于第一电压电平，并且输出信号处于第二值表示输入信号基本上处于第二电压电平。

5. 发明授权

US08159262B1 Impedance compensation in a buffer circuit 有权
标题翻译：缓冲电路中的阻抗补偿
公开(公告)号：US08159262B1
公开(公告)日：2012-04-17
申请号：US13030278
申请日：2011-02-18
申请人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman
发明人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman
IPC分类号： H03K17/16
CPC分类号： H03K19/00384
摘要： A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit having a pull-up portion comprising at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage in the buffer circuit and is operative to generate a first control signal indicating a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage over variations in PVT conditions to which the buffer circuit may be subjected. The compensation circuit further includes a control circuit generating first and second sets of digital control bits for compensating the pull-up and pull-down portions in the output stage over prescribed variations in PVT conditions. The second set of digital control bits is generated based at least on the first set of digital control bits and the first control signal.
摘要翻译：用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括具有包括至少一个PMOS晶体管的上拉部分和包括至少一个NMOS晶体管的下拉部分的监控电路。监视器电路被配置为跟踪缓冲器电路中的输出级的操作，并且可操作以产生第一控制信号，该第一控制信号指示输出级中的相应上拉和下拉部分的至少一个特征的状态，在缓冲电路可能遭受的PVT条件下。补偿电路还包括一个控制电路，产生第一和第二组数字控制位，用于通过PVT条件中规定的变化来补偿输出级中的上拉和下拉部分。至少基于第一组数字控制位和第一控制信号产生第二组数字控制位。

6. 发明授权

US08362803B2 Mode latching buffer circuit 有权
标题翻译：模式锁存缓冲电路
公开(公告)号：US08362803B2
公开(公告)日：2013-01-29
申请号：US13031176
申请日：2011-02-18
申请人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
发明人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K3/356182
摘要： A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.
摘要翻译：电压转换器电路包括适于接收参考第一电压源的输入信号的输入级，适于与第二电压源连接并可操作以至少临时存储输入信号的逻辑状态的第一锁存电路，以及电压钳耦合在输入级和第一锁存电路之间。电压钳可用于将输入级两端的最大电压设定到规定的电平。电压转换器电路在形成在第一锁存电路和电压钳之间的结处的第一输出处产生第一输出信号。第二锁存电路以反馈配置连接到第一输出端。第二锁存电路用于将第一输出信号的逻辑状态保持为至少提供给第二锁存电路的第一控制信号的函数，而与第一电压源的状态无关。

7. 发明申请

US20120212256A1 Mode Latching Buffer Circuit 有权
标题翻译：模式锁存缓冲电路
公开(公告)号：US20120212256A1
公开(公告)日：2012-08-23
申请号：US13031176
申请日：2011-02-18
申请人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
发明人： Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
IPC分类号： H03K19/0175 , H03K5/08
CPC分类号： H03K19/018521 , H03K3/356182
摘要： A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.
摘要翻译：电压转换器电路包括适于接收参考第一电压源的输入信号的输入级，适于与第二电压源连接并可操作以至少临时存储输入信号的逻辑状态的第一锁存电路，以及电压钳耦合在输入级和第一锁存电路之间。电压钳可用于将输入级两端的最大电压设定到规定的电平。电压转换器电路在形成在第一锁存电路和电压钳之间的结处的第一输出处产生第一输出信号。第二锁存电路以反馈配置连接到第一输出端。第二锁存电路用于将第一输出信号的逻辑状态保持为至少提供给第二锁存电路的第一控制信号的函数，而与第一电压源的状态无关。

8. 发明授权

US08598941B2 Hybrid impedance compensation in a buffer circuit 有权
标题翻译：缓冲电路中的混合阻抗补偿
公开(公告)号：US08598941B2
公开(公告)日：2013-12-03
申请号：US13165195
申请日：2011-06-21
申请人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
发明人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
IPC分类号： H01L37/00
CPC分类号： H03F3/3022 , H03F1/308 , H03F1/56 , H03F2200/447
摘要： A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.
摘要翻译：用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。监视器电路包括上拉部分，其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。监视器电路被配置为跟踪缓冲电路的输出级的操作，并且可操作地产生至少第一控制信号，该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。控制电路用于产生作为第一控制信号的函数的一组数字控制位。该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。

9. 发明申请

US20120326768A1 Hybrid Impedance Compensation in a Buffer Circuit 有权
标题翻译：缓冲电路中的混合阻抗补偿
公开(公告)号：US20120326768A1
公开(公告)日：2012-12-27
申请号：US13165195
申请日：2011-06-21
申请人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
发明人： Dipankar Bhattacharya , Ashish V. Shukla , John Christopher Kriz , Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
IPC分类号： H03H11/40
CPC分类号： H03F3/3022 , H03F1/308 , H03F1/56 , H03F2200/447
摘要： A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.
摘要翻译：用于控制至少一个缓冲电路的输出阻抗变化的补偿电路包括监视电路和与监视器电路耦合的控制电路。监视器电路包括上拉部分，其包括至少一个PMOS晶体管和包括至少一个NMOS晶体管的下拉部分。监视器电路被配置为跟踪缓冲电路的输出级的操作，并且可操作地产生至少第一控制信号，该第一控制信号指示输出中相应的上拉和下拉部分的至少一个特性的状态缓冲电路的阶段与缓冲电路可能受到的PVT条件的变化有关。控制电路用于产生作为第一控制信号的函数的一组数字控制位。该组数字控制位可用来补偿缓冲电路的输出级中的上拉和下拉部分超过规定的PVT条件变化。

10. 发明授权

US07106107B2 Reliability comparator with hysteresis 有权
标题翻译：具有迟滞的可靠性比较器
公开(公告)号：US07106107B2
公开(公告)日：2006-09-12
申请号：US11047388
申请日：2005-01-31
申请人： Dipankar Bhattacharya , John Christopher Kriz , Bernard L. Morris , William B. Wilson
发明人： Dipankar Bhattacharya , John Christopher Kriz , Bernard L. Morris , William B. Wilson
IPC分类号： H03K5/22
CPC分类号： H03K3/02337 , H03K3/3565
摘要： A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal. A hysteresis circuit is included in the comparator circuit for selectively controlling a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator. The comparator circuit includes a voltage clamp operative to limit a voltage applied to one or more devices in the control circuit, the comparator, and/or the hysteresis circuit to less than the second voltage.
摘要翻译：比较器电路包括连接到提供第一电压的第一源的参考发生器。参考发生器用于产生参考信号并且包括响应于第一控制信号选择性地以至少第一模式或第二模式操作的控制电路，其中在第一模式中不产生参考信号，并且在第二模式，参考发生器用于产生参考信号。比较器电路还包括连接到提供第二电压的第二源的比较器，第二电压小于第一电压。比较器用于接收参考信号和输入信号，并且产生作为输入信号和参考信号之间的比较的函数的输出信号。比较器电路中包括滞后电路，用于根据比较器的输出信号选择性地控制比较器相对于输入信号的切换阈值。比较器电路包括电压钳位器，用于将施加到控制电路，比较器和/或滞后电路中的一个或多个器件的电压限制为小于第二电压。

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