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1. 发明授权

US07214590B2 Method of forming an electronic device 有权
标题翻译：电子设备的形成方法
公开(公告)号：US07214590B2
公开(公告)日：2007-05-08
申请号：US11098874
申请日：2005-04-05
申请人： Sangwoo Lim , Paul A. Grudowski , Mohamad M. Jahanbani , Hsing H. Tseng , Choh-Fei Yeap
发明人： Sangwoo Lim , Paul A. Grudowski , Mohamad M. Jahanbani , Hsing H. Tseng , Choh-Fei Yeap
IPC分类号： H01L21/336
CPC分类号： H01L21/823462
摘要： A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.
摘要翻译：形成电子器件的方法包括蚀刻第一栅极介电层的一部分以减小该部分内的栅极介电层的厚度。在一个实施例中，未被蚀刻的部分可以被掩模覆盖。在另一个实施例中，不同部分可以在不同时间被蚀刻，以给予第一栅极介电层不同的厚度。在特定实施例中，可以在蚀刻该部分之后在第一栅极电介质层上形成第二栅极电介质层。第二栅极介电层可以具有大于第一栅极介电层的介电常数的介电常数。可以进行随后的栅电极和源/漏区形成以形成晶体管结构。

2. 发明授权

US07402472B2 Method of making a nitrided gate dielectric 失效
标题翻译：制造氮化栅极电介质的方法
公开(公告)号：US07402472B2
公开(公告)日：2008-07-22
申请号：US11067257
申请日：2005-02-25
申请人： Sangwoo Lim , Paul A. Grudowski , Tien Ying Luo , Olubunmi O. Adetutu , Hsing H. Tseng
发明人： Sangwoo Lim , Paul A. Grudowski , Tien Ying Luo , Olubunmi O. Adetutu , Hsing H. Tseng
IPC分类号： H01L21/336
CPC分类号： H01L21/02329 , H01L21/02181 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/3185 , H01L29/4908 , H01L29/511 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
摘要翻译：用氮化步骤和退火处理栅极电介质。之后，进行另外的氮化步骤和退火。第二次氮化和退火导致栅极漏电流密度与最终形成的晶体管的电流驱动之间的关系得到改善。

3. 发明申请

US20060223266A1 Method of forming an electronic device 有权
标题翻译：电子设备的形成方法
公开(公告)号：US20060223266A1
公开(公告)日：2006-10-05
申请号：US11098874
申请日：2005-04-05
申请人： Sangwoo Lim , Paul Grudowski , Mohamad Jahanbani , Hsing Tseng , Choh-Fei Yeap
发明人： Sangwoo Lim , Paul Grudowski , Mohamad Jahanbani , Hsing Tseng , Choh-Fei Yeap
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462
摘要： A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.
摘要翻译：一种形成电子器件的方法包括蚀刻第一栅极电介质层的一部分以减小该部分内的栅极电介质层的厚度。在一个实施例中，未被蚀刻的部分可以被掩模覆盖。在另一个实施例中，不同部分可以在不同时间被蚀刻，以给予第一栅极介电层不同的厚度。在特定实施例中，可以在蚀刻该部分之后在第一栅极电介质层上形成第二栅极电介质层。第二栅极介电层可以具有大于第一栅极介电层的介电常数的介电常数。可以进行随后的栅电极和源/漏区形成以形成晶体管结构。

4. 发明授权

US07126172B2 Integration of multiple gate dielectrics by surface protection 有权
公开(公告)号：US07126172B2
公开(公告)日：2006-10-24
申请号：US10962944
申请日：2004-10-12
申请人： Sangwoo Lim , Laegu Kang , Geoffrey (Choh-Fei) Yeap
发明人： Sangwoo Lim , Laegu Kang , Geoffrey (Choh-Fei) Yeap
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L21/823462
摘要： A multiple gate oxidation process is provided. The process comprises the steps of (a) providing a silicon substrate (203) having a sacrificial oxide layer (207) thereon; (b) depositing and patterning a first layer of photoresist (209) on the sacrificial oxide layer, thereby forming a first region in which the sacrificial oxide layer is exposed; (c) etching the exposed sacrificial oxide layer within the first region, thereby forming a first etched region; (d) growing a first oxide layer (211) within the first etched region; (e) depositing and patterning a second layer of photoresist (213) on the sacrificial oxide layer and first oxide layer, thereby forming a second region in which the sacrificial oxide layer is exposed; (f) etching the exposed sacrificial oxide layer within the second region, thereby forming a second etched region; and (g) growing a second oxide layer (215) within the second etched region.

5. 发明申请

US20060084220A1 Differentially nitrided gate dielectrics in CMOS fabrication process 审中-公开
标题翻译： CMOS制造工艺中的差分氮化栅极电介质
公开(公告)号：US20060084220A1
公开(公告)日：2006-04-20
申请号：US10965963
申请日：2004-10-15
申请人： Sangwoo Lim , Paul Grudowski , Dejan Jovanovic , Choh-Fei Yeap
发明人： Sangwoo Lim , Paul Grudowski , Dejan Jovanovic , Choh-Fei Yeap
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/823807
摘要： A semiconductor fabrication process includes forming a first plasma nitrided oxide (PNO) gate dielectric overlying a first region of a semiconductor substrate. A second PNO gate dielectric is formed overlying a second region of the substrate. The nitrogen concentration of the second PNO differs from the nitrogen concentration of the first PNO. A PMOS transistor is formed overlying the first substrate region and an NMOS transistor overlying the second substrate region. Prior to forming the first PNO gate dielectric, a mobility enhancing channel region may be formed overlying the first substrate region. Forming the mobility enhancing channel region may include forming a compressively stressed silicon germanium film overlying the first substrate region.
摘要翻译：半导体制造工艺包括形成覆盖在半导体衬底的第一区域上的第一等离子体氮化氧化物（PNO）栅极电介质。在衬底的第二区域上形成第二PNO栅极电介质。第二PNO的氮浓度与第一PNO的氮浓度不同。形成在第一衬底区域上方的PMOS晶体管和覆盖第二衬底区域的NMOS晶体管。在形成第一PNO栅极电介质之前，可以形成覆盖在第一衬底区域上的迁移率增强沟道区。形成迁移率增强沟道区域可以包括形成覆盖在第一衬底区域上的压缩应力的硅锗膜。

6. 发明授权

US07041562B2 Method for forming multiple gate oxide thickness utilizing ashing and cleaning 失效
标题翻译：使用灰化和清洁形成多个栅极氧化物厚度的方法
公开(公告)号：US07041562B2
公开(公告)日：2006-05-09
申请号：US10696079
申请日：2003-10-29
申请人： Sangwoo Lim , Yongjoo Jeon , Choh-Fei Yeap
发明人： Sangwoo Lim , Yongjoo Jeon , Choh-Fei Yeap
IPC分类号： H01L21/311
CPC分类号： H01L21/02054 , H01L21/823462 , H01L21/823857 , Y10S438/981
摘要： Embodiments of the present invention relate to semiconductor structures having multiple gate dielectric structures. One embodiment forms semiconductor devices in multiple regions having different dielectric thicknesses where the interface between the gate dielectric and the semiconductor substrate is protected to result in an improved (e.g. less rough) interface. One embodiment includes forming a dielectric layer overlying a substrate, partially etching the dielectric layer in at least one of the multiple regions, and ashing the dielectric layer. The remaining portion of the dielectric layer (due to the partial etch) may then help protect the underlying substrate from damage during a subsequent preclean. Afterwards, in one embodiment, the gate dielectric layer is grown to achieve a target gate dielectric thickness in at least one of the regions. This may also help further densify the gate dielectric layer. Processing may then be continued to form semiconductor devices in each of the multiple regions.
摘要翻译：本发明的实施例涉及具有多个栅介质结构的半导体结构。一个实施例在具有不同介电厚度的多个区域中形成半导体器件，其中栅极电介质和半导体衬底之间的界面被保护以导致改进的（例如较不粗糙的）界面。一个实施例包括形成覆盖衬底的电介质层，部分地蚀刻多个区域中的至少一个中的电介质层，以及灰化介电层。电介质层的剩余部分（由于局部蚀刻）可能有助于保护下一层衬底在随后的预清洗过程中不被损坏。之后，在一个实施例中，生长栅介质层以在至少一个区域中实现目标栅介质厚度。这还可以有助于进一步增强栅极介质层的密度。然后可以继续处理以在多个区域的每一个中形成半导体器件。

7. 发明申请

US20050093063A1 Multiple gate dielectric structure and method for forming 失效
标题翻译：多栅电介质结构及其形成方法
公开(公告)号：US20050093063A1
公开(公告)日：2005-05-05
申请号：US10696079
申请日：2003-10-29
申请人： Sangwoo Lim , Yongjoo Jeon , Choh-Fei Yeap
发明人： Sangwoo Lim , Yongjoo Jeon , Choh-Fei Yeap
IPC分类号： H01L21/02 , H01L21/306 , H01L21/8234 , H01L21/8238 , H01L27/01 , H01L21/31 , H01L21/469 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/02054 , H01L21/823462 , H01L21/823857 , Y10S438/981
摘要： Embodiments of the present invention relate to semiconductor structures having multiple gate dielectric structures. One embodiment forms semiconductor devices in multiple regions having different dielectric thicknesses where the interface between the gate dielectric and the semiconductor substrate is protected to result in an improved (e.g. less rough) interface. One embodiment includes forming a dielectric layer overlying a substrate, partially etching the dielectric layer in at least one of the multiple regions, and ashing the dielectric layer. The remaining portion of the dielectric layer (due to the partial etch) may then help protect the underlying substrate from damage during a subsequent preclean. Afterwards, in one embodiment, the gate dielectric layer is grown to achieve a target gate dielectric thickness in at least one of the regions. This may also help further densify the gate dielectric layer. Processing may then be continued to form semiconductor devices in each of the multiple regions.
摘要翻译：本发明的实施例涉及具有多个栅介质结构的半导体结构。一个实施例在具有不同介电厚度的多个区域中形成半导体器件，其中栅极电介质和半导体衬底之间的界面被保护以导致改进的（例如较不粗糙的）界面。一个实施例包括形成覆盖衬底的电介质层，部分地蚀刻多个区域中的至少一个中的电介质层，以及灰化介电层。电介质层的剩余部分（由于局部蚀刻）可能有助于保护下一层衬底在随后的预清洗过程中不被损坏。之后，在一个实施例中，生长栅介质层以在至少一个区域中实现目标栅介质厚度。这还可以有助于进一步增强栅极介质层的密度。然后可以继续处理以在多个区域的每一个中形成半导体器件。

8. 发明授权

US07504289B2 Process for forming an electronic device including transistor structures with sidewall spacers 失效
标题翻译：用于形成包括具有侧壁间隔物的晶体管结构的电子器件的工艺
公开(公告)号：US07504289B2
公开(公告)日：2009-03-17
申请号：US11258781
申请日：2005-10-26
申请人： Sangwoo Lim , Stanley L. Filipiak , Paul A. Grudowski , Venkat R. Kolagunta
发明人： Sangwoo Lim , Stanley L. Filipiak , Paul A. Grudowski , Venkat R. Kolagunta
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/7843
摘要： An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure including a second gate electrode surrounding a second sidewall spacer having second stress. The first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode and the second sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode, wherein the first stress has a lower value as compared to the second stress. More than one process can be used to form the electronic device.
摘要翻译：电子器件可以包括第一晶体管结构，其包括由具有第一应力的第一侧壁间隔物围绕的第一栅电极和包括围绕具有第二应力的第二侧壁间隔物的第二栅电极的第二晶体管结构。与围绕第一栅电极的任何其它侧壁间隔物相比，第一侧壁间隔物是围绕第一栅电极或更靠近的侧壁间隔物的唯一侧壁间隔物，并且第二侧壁间隔物是仅围绕第二栅电极的侧壁间隔物与围绕第二栅电极的任何其它侧壁间隔物相比，其中第一应力具有与第二应力相比较低的值。可以使用多个过程来形成电子设备。

9. 发明申请

US20070090455A1 Electronic device including transistor structures with sidewall spacers and a process for forming the electronic device 失效
标题翻译：电子器件包括具有侧壁间隔物的晶体管结构和用于形成电子器件的工艺
公开(公告)号：US20070090455A1
公开(公告)日：2007-04-26
申请号：US11258781
申请日：2005-10-26
申请人： Sangwoo Lim , Stanley Filipiak , Paul Grudowski , Venkat Kolagunta
发明人： Sangwoo Lim , Stanley Filipiak , Paul Grudowski , Venkat Kolagunta
IPC分类号： H01L29/76 , H01L21/8238 , H01L21/336 , H01L27/12 , H01L29/94 , H01L27/01 , H01L31/00 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/7843
摘要： An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure including a second gate electrode surrounding a second sidewall spacer having second stress. The first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode and the second sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode, wherein the first stress has a lower value as compared to the second stress. More than one process can be used to form the electronic device.
摘要翻译：电子器件可以包括第一晶体管结构，其包括由具有第一应力的第一侧壁间隔物围绕的第一栅电极和包括围绕具有第二应力的第二侧壁间隔物的第二栅电极的第二晶体管结构。与围绕第一栅电极的任何其它侧壁间隔物相比，第一侧壁间隔物是围绕第一栅电极或更靠近的侧壁间隔物的唯一侧壁间隔物，并且第二侧壁间隔物是仅围绕第二栅电极的侧壁间隔物与围绕第二栅电极的任何其它侧壁间隔物相比，其中第一应力具有与第二应力相比较低的值。可以使用多个过程来形成电子设备。

10. 发明申请

US20060194423A1 Method of making a nitrided gate dielectric 失效
标题翻译：制造氮化栅极电介质的方法
公开(公告)号：US20060194423A1
公开(公告)日：2006-08-31
申请号：US11067257
申请日：2005-02-25
申请人： Sangwoo Lim , Paul Grudowski , Tien Luo , Olubunmi Adetutu , Hsing Tseng
发明人： Sangwoo Lim , Paul Grudowski , Tien Luo , Olubunmi Adetutu , Hsing Tseng
IPC分类号： H01L21/3205 , H01L21/31 , H01L21/336
CPC分类号： H01L21/02329 , H01L21/02181 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/3185 , H01L29/4908 , H01L29/511 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
摘要翻译：用氮化步骤和退火处理栅极电介质。之后，进行另外的氮化步骤和退火。第二次氮化和退火导致栅极漏电流密度与最终形成的晶体管的电流驱动之间的关系得到改善。

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