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1. 发明授权

US08323412B2 Substrate support, substrate processing device and method of placing a substrate 有权
标题翻译：基板支撑，基板处理装置和放置基板的方法
公开(公告)号：US08323412B2
公开(公告)日：2012-12-04
申请号：US12108320
申请日：2008-04-23
申请人： Dieter Haas , Thomas Berger , Simon Lau
发明人： Dieter Haas , Thomas Berger , Simon Lau
IPC分类号： C23C16/00 , B05C13/00
CPC分类号： H01L21/68714 , H01L21/68 , Y10T29/49998
摘要： A substrate support for supporting a substrate in a processing chamber comprises a frame for carrying the substrate, at least a first fastening means fixedly attached to the frame for aligning the substrate relative to the frame, and at least a second fastening means movably attached to the frame, the second fastening means being movable relative to the frame and/or the substrate. Furthermore, a processing device comprises an edge exclusion projecting over a portion of the surface of the substrate in order to prevent processing of the portion of the surface of the substrate. A part of the edge exclusion may be moved into a gap between the edge(s) of the substrate and the frame element of the substrate support to form a labyrinth seal between the frame element and the edge of the substrate. A method of placing the substrate on the substrate support is also disclosed.
摘要翻译：用于在处理室中支撑衬底的衬底支撑件包括用于承载衬底的框架，至少一个固定地连接到框架上用于使衬底相对于框架对准的第一紧固装置，以及至少一个第二紧固装置，第二紧固装置可相对于框架和/或基板移动。此外，处理装置包括在衬底表面的一部分上突出的边缘排除，以防止衬底的表面部分的处理。边缘排除的一部分可以移动到基板的边缘和基板支撑件的框架元件之间的间隙中，以在框架元件和基板的边缘之间形成迷宫式密封。还公开了将衬底放置在衬底支撑件上的方法。

2. 发明申请

US20080295773A1 SUBSTRATE SUPPORT, SUBSTRATE PROCESSING DEVICE AND METHOD OF PLACING A SUBSTRATE 有权
标题翻译：基板支撑，基板处理装置和放置基板的方法
公开(公告)号：US20080295773A1
公开(公告)日：2008-12-04
申请号：US12108320
申请日：2008-04-23
申请人： Dieter Haas , Thomas Berger , Simon Lau
发明人： Dieter Haas , Thomas Berger , Simon Lau
IPC分类号： C23C16/54
CPC分类号： H01L21/68714 , H01L21/68 , Y10T29/49998
摘要： A substrate support for supporting a substrate in a processing chamber comprises a frame for carrying the substrate, at least a first fastening means fixedly attached to the frame for aligning the substrate relative to the frame, and at least a second fastening means movably attached to the frame, the second fastening means being movable relative to the frame and/or the substrate. Furthermore, a processing device comprises an edge exclusion projecting over a portion of the surface of the substrate in order to prevent processing of the portion of the surface of the substrate. A part of the edge exclusion may be moved into a gap between the edge(s) of the substrate and the frame element of the substrate support to form a labyrinth seal between the frame element and the edge of the substrate. A method of placing the substrate on the substrate support is also disclosed.
摘要翻译：用于在处理室中支撑衬底的衬底支撑件包括用于承载衬底的框架，至少一个固定地连接到框架上用于使衬底相对于框架对准的第一紧固装置，以及至少一个第二紧固装置，第二紧固装置可相对于框架和/或基板移动。此外，处理装置包括在衬底表面的一部分上突出的边缘排除，以防止衬底的表面部分的处理。边缘排除的一部分可以移动到基板的边缘和基板支撑件的框架元件之间的间隙中，以在框架元件和基板的边缘之间形成迷宫式密封。还公开了将衬底放置在衬底支撑件上的方法。

3. 发明授权

US06370266B1 Financial document processing system and method of operating a financial document processing system to verify zone coordinates 有权
标题翻译：财务文件处理系统和操作财务文件处理系统的方法来验证区域坐标
公开(公告)号：US06370266B1
公开(公告)日：2002-04-09
申请号：US09292893
申请日：1999-04-16
申请人： Simon Lau , Hui Wu
发明人： Simon Lau , Hui Wu
IPC分类号： G06K900
CPC分类号： G06K17/00
摘要： A financial document processing system has a transport path and an I/O device disposed along the transport path. The system comprises an input device for receiving a set of zone coordinates. An I/O device is disposed along the transport path. A memory is provided for storing a plurality of sets of rules. A processor is provided for (i) obtaining one set of the plurality of sets of rules based upon type of the I/O device, and (ii) applying the one set of rules against the set of zone coordinates to determine if the set of zone coordinates is acceptable. The processor then adjusts the set of zone coordinates based upon application of the set of rules against the set of zone coordinates.
摘要翻译：财务文件处理系统具有沿传送路径设置的传送路径和I / O设备。该系统包括用于接收一组区域坐标的输入装置。 I / O设备沿传送路径设置。提供存储多个规则集的存储器。提供了一种处理器，用于（i）基于I / O设备的类型来获得多组规则集合中的一组，以及（ii）针对所述一组区域坐标应用一组规则，以确定该组区域坐标是可以接受的。然后，处理器基于对该组坐标系的一组规则的应用来调整该区域坐标集合。

4. 发明授权

US6000013A Method and apparatus for connecting memory chips to form a cache memory by assigning each chip a unique identification characteristic 失效
标题翻译：用于通过为每个芯片分配独特的识别特征来连接存储器芯片以形成高速缓存的方法和装置
公开(公告)号：US6000013A
公开(公告)日：1999-12-07
申请号：US689875
申请日：1996-08-15
申请人： Simon Lau , Pradip Banerjee , Atul V. Ghia
发明人： Simon Lau , Pradip Banerjee , Atul V. Ghia
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0846 , G06F12/0893
摘要： The present invention includes a central processing unit (CPU) coupled to a bus. Cache memory devices are coupled to the bus to receive memory requests from the CPU. Each of the cache memory devices includes a cache memory which is coupled to the controller circuit. The controller circuit provides control signals, which enable the cache memory to execute a memory operation requested by the CPU. The controller circuit is coupled to receive predefined address bits comprising memory addresses and memory requests issued by the CPU. Each of the controller circuits disposed in each cache memory device is further coupled to receive an identification number unique to each of the cache memory devices coupled to the bus. The controller circuits disposed in each of the cache memory devices compares the unique identification number with the predefined address bits, such that if the identification number and the predefined address bits match, the controller circuit provides control signals to enable its cache memory to execute the memory operation requested by the CPU at the cache memory location corresponding to the main memory address. In the event the identification does not match the predefined bits of the address, the memory controller circuit does not provide control signals to enable the memory to execute the memory operation and disables output driver circuits disposed within the cache.
摘要翻译：本发明包括耦合到总线的中央处理单元（CPU）。缓存存储器件耦合到总线以从CPU接收存储器请求。每个高速缓冲存储器件包括耦合到控制器电路的高速缓冲存储器。控制器电路提供控制信号，使得高速缓冲存储器能够执行由CPU请求的存储器操作。控制器电路被耦合以接收包括由CPU发出的存储器地址和存储器请求的预定义的地址位。设置在每个高速缓冲存储器设备中的每个控制器电路还被耦合以接收与耦合到总线的每个高速缓冲存储器设备唯一的识别号码。布置在每个高速缓冲存储器设备中的控制器电路将唯一标识号与预定义的地址位进行比较，使得如果标识号和预定义的地址位匹配，则控制器电路提供控制信号以使其高速缓冲存储器能够执行存储器 CPU在与主存储器地址相对应的缓存存储器位置处请求的操作。在识别与地址的预定义比特不匹配的情况下，存储器控制器电路不提供控制信号以使得存储器能够执行存储器操作并且禁用设置在高速缓存内的输出驱动器电路。

5. 发明授权

US06826307B1 Contrast determining apparatus and methods 有权
标题翻译：对比度测定装置及方法
公开(公告)号：US06826307B1
公开(公告)日：2004-11-30
申请号：US09254262
申请日：1999-03-24
申请人： Simon Lau , Brinley Rhys Roberts
发明人： Simon Lau , Brinley Rhys Roberts
IPC分类号： G06K948
CPC分类号： G06T7/40 , G06T2207/30164
摘要： The contrast determination apparatus includes illuminating light sources (12) and an image sensor (26) i.e. a 2-D CCD for capturing a two-dimensional image of e.g. a marked wire (32) on a holder (34), the captured image being sampled over the mark and the background. The sensor includes an optical system (28,30) selected with regard to the character size of the marks so that the field of view of the sensor is sufficient to contain a complete character as well as a generous amount of background. An area of the captured image is designated in which the samples for contrast measurement are to be taken, and a processor (24) takes the pixel values from the image which are thresholded to categorise them as “black”, or “white”, thus forming a two-tone image. Aggregates or averages of the “black” and “white” pixel values are used to derive the contrast measurement according to the formula: (Imax−Imin)/Imax where Imax is the average value of the “white” pixels and Imin the average value of the “black” pixels.
摘要翻译：对比度确定装置包括照明光源（12）和图像传感器（26），即用于捕获例如二维图像的二维图像的2-D CCD。在保持器（34）上的标记线（32），捕获的图像在标记和背景上被采样。传感器包括关于标记的字符尺寸选择的光学系统（28,30），使得传感器的视场足以包含完整的字符以及大量的背景。指定拍摄图像的区域，其中将采取用于对比度测量的样本，并且处理器（24）从被阈值化的图像中取出被分类为“黑色”或“白色”的像素值，因此形成双色图像。 “黑色”和“白色”像素值的聚合或平均值用于根据以下公式导出对比度测量：（Imax-Imin）/ Imax，其中Imax是“白”像素的平均值，Imin在平均值的“黑色”像素。

6. 发明授权

US10636687B2 Apparatus for transportation of a substrate carrier in a vacuum chamber, system for vacuum processing of a substrate, and method for transportation of a substrate carrier in a vacuum chamber 有权
公开(公告)号：US10636687B2
公开(公告)日：2020-04-28
申请号：US16062596
申请日：2016-01-18
申请人： Applied Materials, Inc. , Simon Lau , Wolfgang Buschbeck
发明人： Simon Lau , Wolfgang Buschbeck
IPC分类号： B65G35/00 , C23C14/50 , H01L21/677 , C23C14/35 , C23C14/56
CPC分类号： H01L21/67709 , C23C14/351 , C23C14/50 , C23C14/568 , H01L21/6776 , H01L21/67715
摘要： An apparatus for transportation of a substrate carrier in a vacuum chamber is provided. The apparatus includes a first track providing a first transportation path for the substrate carrier, and a transfer device configured for contactlessly moving the substrate carrier from a first position on the first track to one or more second positions away from the first track. The one or more second positions include at least one of a position on a second track and a process position for processing of a substrate. The transfer device includes at least one first magnet device configured to provide a magnetic force acting on the substrate carrier to contactlessly move the substrate carrier from the first position to the one or more second positions.

7. 发明授权

US6144011A Laser marking apparatus and methods 失效
标题翻译：激光打标设备及方法
公开(公告)号：US6144011A
公开(公告)日：2000-11-07
申请号：US125689
申请日：1998-08-24
申请人： John Moss , Simon Lau , David Keston Phillips
发明人： John Moss , Simon Lau , David Keston Phillips
IPC分类号： G06K1/12 , B23K26/36
CPC分类号： G06K1/126 , B41M5/26 , B41M5/262 , B41M5/267
摘要： A method and apparatus for laser marking a moving workpiece such as a wire or cable directs a substantially constant rapidly pulsed laser beam at a frequency of at least 15 Hz towards a low inertia, low mass rotatable mask with character apertures disposed around its periphery. The mask is driven asynchronously to present successive characters with each pulse to form a composite image.
摘要翻译： PCT No.PCT / GB97 / 00497 Sec。 371日期：1998年8月24日 102（e）1998年8月24日PCT 1997年2月24日PCT公布。出版物WO97 / 31324 PCT 日期1997年8月28日一种用于激光标记诸如线或电缆的移动工件的方法和装置将基本上恒定的快速脉冲激光束以至少15Hz的频率朝向具有设置的字符孔的低惯性，低质量可旋转掩模围绕其周边。该掩模被异步地驱动以呈现每个脉冲的连续字符以形成合成图像。

8. 发明授权

US5502670A Single cycle flush for RAM memory 失效
标题翻译： RAM存储器的单周期刷新
公开(公告)号：US5502670A
公开(公告)日：1996-03-26
申请号：US346739
申请日：1994-11-30
申请人： Pradip Banerjee , Atul V. Ghia , Simon Lau
发明人： Pradip Banerjee , Atul V. Ghia , Simon Lau
IPC分类号： G11C11/41 , G11C7/20 , G11C7/00
CPC分类号： G11C7/20
摘要： The present invention provides methods and apparatus for resetting all of the cells in a random access memory (RAM) during one clock cycle without requiring ancillary drivers. At the start of the reset cycle, each column in the memory array is selected to receive the reset value and then each data line in the array is driven low while the inverse of the data line is driven high. After a first predetermined delay, each word line is driven high and all of the memory cells are thus reset. The word lines are then driven low and after a second predetermined delay, the data lines are driven back to a high value. In this manner, each cell in the memory array is reset during one clock cycle.
摘要翻译：本发明提供了用于在一个时钟周期内复位随机存取存储器（RAM）中的所有单元的方法和装置，而不需要辅助驱动器。在复位周期开始时，选择存储器阵列中的每列以接收复位值，然后数组中的每个数据线被驱动为低电平，而数据线的反相驱动为高电平。在第一预定延迟之后，每个字线被驱动为高电平，并且所有存储器单元因此被复位。然后，字线被驱动为低电平并且在第二预定延迟之后，数据线被驱动回到高值。以这种方式，存储器阵列中的每个单元在一个时钟周期期间被复位。

9. 发明授权

US5577228A Digital circuit for performing multicycle addressing in a digital memory 失效
标题翻译：用于在数字存储器中执行多周期寻址的数字电路
公开(公告)号：US5577228A
公开(公告)日：1996-11-19
申请号：US351900
申请日：1994-12-08
申请人： Pradip Banerjee , Atul V. Ghia , Simon Lau , Patrick Chuang
发明人： Pradip Banerjee , Atul V. Ghia , Simon Lau , Patrick Chuang
IPC分类号： G06F12/08 , G06F9/34
CPC分类号： G06F12/0893 , Y02B60/1225
摘要： The architecture of the cache memory of the present invention includes a data RAM, a TAG RAM, a controller and pad logic on a single integrated circuit chip. The cache memory is coupled to a CPU and a memory bus controller over a host bus. The host bus receives read data from the cache memory and provides write data to the cache memory. The cache memory controller provides signals to the memory bus controller to indicate whether data accessed by the CPU resides in the cache memory. The present invention increases memory speed by allowing circuit elements in the cache memory to operate during both phases of a system clock signal.
摘要翻译：本发明的高速缓冲存储器的结构在单个集成电路芯片上包括数据RAM，TAG RAM，控制器和焊盘逻辑。缓存存储器通过主机总线耦合到CPU和存储器总线控制器。主机总线从高速缓冲存储器接收读取数据，并向高速缓冲存储器提供写入数据。高速缓冲存储器控制器向存储器总线控制器提供信号以指示CPU访问的数据是否驻留在高速缓冲存储器中。本发明通过允许高速缓冲存储器中的电路元件在系统时钟信号的两个相位期间操作来提高存储器速度。

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