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1. 发明授权

US5502670A Single cycle flush for RAM memory 失效
标题翻译： RAM存储器的单周期刷新
公开(公告)号：US5502670A
公开(公告)日：1996-03-26
申请号：US346739
申请日：1994-11-30
申请人： Pradip Banerjee , Atul V. Ghia , Simon Lau
发明人： Pradip Banerjee , Atul V. Ghia , Simon Lau
IPC分类号： G11C11/41 , G11C7/20 , G11C7/00
CPC分类号： G11C7/20
摘要： The present invention provides methods and apparatus for resetting all of the cells in a random access memory (RAM) during one clock cycle without requiring ancillary drivers. At the start of the reset cycle, each column in the memory array is selected to receive the reset value and then each data line in the array is driven low while the inverse of the data line is driven high. After a first predetermined delay, each word line is driven high and all of the memory cells are thus reset. The word lines are then driven low and after a second predetermined delay, the data lines are driven back to a high value. In this manner, each cell in the memory array is reset during one clock cycle.
摘要翻译：本发明提供了用于在一个时钟周期内复位随机存取存储器（RAM）中的所有单元的方法和装置，而不需要辅助驱动器。在复位周期开始时，选择存储器阵列中的每列以接收复位值，然后数组中的每个数据线被驱动为低电平，而数据线的反相驱动为高电平。在第一预定延迟之后，每个字线被驱动为高电平，并且所有存储器单元因此被复位。然后，字线被驱动为低电平并且在第二预定延迟之后，数据线被驱动回到高值。以这种方式，存储器阵列中的每个单元在一个时钟周期期间被复位。

2. 发明授权

US4817054A High speed RAM based data serializers 失效
标题翻译：高速RAM数据串行器
公开(公告)号：US4817054A
公开(公告)日：1989-03-28
申请号：US805164
申请日：1985-12-04
申请人： Pradip Banerjee , Paul D. Keswick
发明人： Pradip Banerjee , Paul D. Keswick
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1018
摘要： Multiple bit parallel data serializers are described for accessing data serially through a port at high video data rates. The serializer preferably comprises a buffer array for storing data at a plurality of SRAM memory locations, sense amplifiers for sensing the stored data, an address decoder for selecting a predetermined memory location of the buffer array for data access by the sense amplifiers, a data latch for the latched buffering of data prior to output to the serial port and a control gate for enabling the gated transfer of data between the sense amplifiers and the output latch.
摘要翻译：描述了用于以高视频数据速率串行访问数据的多位并行数据串行器。串行器优选地包括用于在多个SRAM存储器位置存储数据的缓冲器阵列，用于感测存储的数据的读出放大器，用于选择由读出放大器进行数据存取的缓冲器阵列的预定存储器位置的地址解码器，数据锁存器用于在输出到串行端口之前锁存的数据缓冲和用于使能在读出放大器和输出锁存器之间进行门控传输数据的控制门。

3. 发明授权

US5617563A Duty cycle independent tunable clock 失效
标题翻译：占空比独立可调谐时钟
公开(公告)号：US5617563A
公开(公告)日：1997-04-01
申请号：US334687
申请日：1994-11-04
申请人： Pradip Banerjee , Patrick Chuang , Atul V. Ghia
发明人： Pradip Banerjee , Patrick Chuang , Atul V. Ghia
IPC分类号： H03K5/05 , G06F1/08 , G06F1/10
CPC分类号： G06F1/10 , G06F1/08
摘要： An internal clock that generates a signal from a system clock is provided. The signal generated by the internal clock has a duty cycle that is independent of the system clock. The internal clock may be tuned to provide a desired duty cycle that corresponds to the period required for an operation such as a write to memory. The internal clock may provide a duty cycle that is longer or shorter than the system clock. The signal generated by the internal clock has the same period as the signal generated by the system clock to maintain synchronization of system operations.
摘要翻译：提供从系统时钟产生信号的内部时钟。由内部时钟产生的信号具有独立于系统时钟的占空比。可以调整内部时钟以提供对应于诸如写入存储器的操作所需的周期的期望的占空比。内部时钟可以提供比系统时钟更长或更短的占空比。由内部时钟产生的信号与系统时钟产生的信号具有相同的周期，以保持系统操作的同步。

4. 发明授权

US5537355A Scheme to test/repair multiple large RAM blocks 失效
标题翻译：测试/修复多个大型RAM块的方案
公开(公告)号：US5537355A
公开(公告)日：1996-07-16
申请号：US346740
申请日：1994-11-30
申请人： Pradip Banerjee , Atul V. Ghia , Patrick Chuang
发明人： Pradip Banerjee , Atul V. Ghia , Patrick Chuang
IPC分类号： G11C29/00 , G11C29/48 , G11C29/56 , G06F11/22
CPC分类号： G11C29/48
摘要： The method and apparatus of the present invention provides an interface between a testing device and a random access memory (RAM). The RAM comprises two types of RAM, a TAG RAM and a data RAM. In normal operation, the TAG RAM is not coupled to any devices external to the RAM. Thus, to test the TAG RAM, means must be provided to couple the testing device with the RAG RAM. One possible configuration for interface the TAG RAM with the testing device is to dedicate a line from the testing device to the TAG RAM for each output pin of the testing device, which significantly increases the size of the chip. To reduce this increase in size, according to the present invention, the write lines from the testing device share the bus used by the TAG RAM during normal operation. A multiplexer selects between the testing data and normal address data to insure the integrity of data over the bus. By sharing lines according to the present invention, a TAG RAM may be interfaced to a testing device with a minimum expansion of chip size.
摘要翻译：本发明的方法和装置提供了测试设备和随机存取存储器（RAM）之间的接口。 RAM包括两种类型的RAM，TAG RAM和数据RAM。在正常操作中，TAG RAM不耦合到RAM外部的任何设备。因此，为了测试TAG RAM，必须提供将测试设备与RAG RAM耦合的手段。用于将TAG RAM与测试设备接口的一种可能的配置是将测试设备的线路专用于测试设备的每个输出引脚的TAG RAM，这显着增加了芯片的尺寸。为了减小这种尺寸的增加，根据本发明，来自测试装置的写入线在正常操作期间共享由TAG RAM使用的总线。复用器在测试数据和正常地址数据之间进行选择，以确保总线上数据的完整性。通过共享根据本发明的线路，TAG RAM可以以最小的芯片尺寸扩展接口连接到测试设备。

5. 发明授权

US5459416A Sense amplifier common mode dip filter circuit to avoid false misses 失效
标题翻译：感应放大器共模滤波电路，避免错过
公开(公告)号：US5459416A
公开(公告)日：1995-10-17
申请号：US336523
申请日：1994-11-09
申请人： Atul V. Ghia , Pradip Banerjee , Patrick Chuang
发明人： Atul V. Ghia , Pradip Banerjee , Patrick Chuang
IPC分类号： G06F11/00 , G06F11/16 , G06F12/08 , G11C15/00 , G11C29/38 , H03K5/08 , H04B1/10
CPC分类号： G06F11/1608 , G11C15/00 , G11C29/38 , G06F12/0895
摘要： A high speed compare circuit includes a plurality of bit compare block circuits (0 through N) which are coupled in a wired OR configuration to a match line. Each bit compare block (0 through N) includes a compare circuit for receiving a bit and its complement from word A and a corresponding bit and its complement from word B. The compare circuit includes an output line which is normally maintained high to indicate that a match exists. The output line is coupled to a common mode dip filter which is comprised of N and P channel transistors. The output line of the compare circuit is coupled to the gates of a first and a second P channel transistor. The first P channel transistor is coupled to V.sub.cc, and the second P channel transistor is coupled in series to the first P channel transistor. The output line from the compare circuit is also coupled to the gate of an N channel transistor coupled in series with the first and second P channel transistors. The N channel transistor is also coupled to ground. A third P channel transistor is electrically coupled between the first and the second P channel transistors and to ground. A dip filter output line (referred to herein as "compare out") is coupled between the second P channel transistor and the N channel transistor, as well as to the gate of the third P channel transistor. In operation, the common mode dip filter of the present invention filters relatively short duration voltage dips from the output of the compare circuit. These transient voltage dips may be generated through the use of, for example, sense amplifiers to sense memory locations to retrieve words to be compared by the present invention.
摘要翻译：高速比较电路包括以有线OR配置耦合到匹配线的多个位比较块电路（0至N）。每个位比较块（0到N）包括用于从字A接收位和其补码的比较电路，以及来自字B的对应位及其补码。比较电路包括通常保持为高的输出线，以指示a 比赛存在输出线耦合到由N和P沟道晶体管组成的共模dip滤波器。比较电路的输出线耦合到第一和第二P沟道晶体管的栅极。第一P沟道晶体管耦合到Vcc，第二P沟道晶体管串联耦合到第一P沟道晶体管。来自比较电路的输出线也耦合到与第一和第二P沟道晶体管串联耦合的N沟道晶体管的栅极。 N沟道晶体管也耦合到地。第三P沟道晶体管电耦合在第一和第二P沟道晶体管之间并接地。 dip滤波器输出线（在本文中称为“比较输出”）耦合在第二P沟道晶体管和N沟道晶体管之间，以及耦合到第三P沟道晶体管的栅极。在操作中，本发明的共模浸渍滤波器从比较电路的输出滤波相对短的持续时间的电压骤降。这些瞬态电压骤降可以通过使用例如读出放大器来产生，以感测存储器位置以检索本发明要比较的字。

6. 发明授权

US4837746A Method and apparatus for resetting a video SRAM 失效
标题翻译：复位视频SRAM的方法和装置
公开(公告)号：US4837746A
公开(公告)日：1989-06-06
申请号：US805158
申请日：1985-12-04
申请人： Pradip Banerjee , Paul D. Keswick
发明人： Pradip Banerjee , Paul D. Keswick
IPC分类号： G11C7/10 , G11C7/20
CPC分类号： G11C7/20 , G11C7/1006 , G11C7/1078
摘要： A method and apparatus for resetting a SRAM in a single DRAM-SRAM transfer cycle in a graphics system is described comprising a SRAM address decoder, a DRAM data input buffer, a reset data register and data lines. In operation, reset data is transferred into the DRAM data input buffer. Thereafter, the SRAM is isolated from the address decoder and the data lines and the reset data is transferred from the DRAM data input buffer into the reset data register. Then data is transferred in parallel between the DRAM and the SRAM. Upon completion of the transfer of data between the DRAM and the SRAM, the SRAM is recoupled to the data lines. After the SRAM is recoupled to the data lines, the reset data is transferred in parallel to the SRAM. Upon the transfer of the reset data to the SRAM, the system is returned to its pre-transfer cycle condition.
摘要翻译：描述了一种用于在图形系统中的单个DRAM-SRAM传输周期中复位SRAM的方法和装置，其包括SRAM地址解码器，DRAM数据输入缓冲器，复位数据寄存器和数据线。在操作中，复位数据被传送到DRAM数据输入缓冲器。此后，SRAM与地址解码器隔离，数据线和复位数据从DRAM数据输入缓冲器传送到复位数据寄存器。然后数据在DRAM和SRAM之间并行传输。在DRAM和SRAM之间完成数据传送时，SRAM被重新耦合到数据线。在将SRAM重新连接到数据线之后，复位数据与SRAM并行传输。在将复位数据传送到SRAM时，系统返回到其预传送周期状态。

7. 发明授权

US6000013A Method and apparatus for connecting memory chips to form a cache memory by assigning each chip a unique identification characteristic 失效
标题翻译：用于通过为每个芯片分配独特的识别特征来连接存储器芯片以形成高速缓存的方法和装置
公开(公告)号：US6000013A
公开(公告)日：1999-12-07
申请号：US689875
申请日：1996-08-15
申请人： Simon Lau , Pradip Banerjee , Atul V. Ghia
发明人： Simon Lau , Pradip Banerjee , Atul V. Ghia
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0846 , G06F12/0893
摘要： The present invention includes a central processing unit (CPU) coupled to a bus. Cache memory devices are coupled to the bus to receive memory requests from the CPU. Each of the cache memory devices includes a cache memory which is coupled to the controller circuit. The controller circuit provides control signals, which enable the cache memory to execute a memory operation requested by the CPU. The controller circuit is coupled to receive predefined address bits comprising memory addresses and memory requests issued by the CPU. Each of the controller circuits disposed in each cache memory device is further coupled to receive an identification number unique to each of the cache memory devices coupled to the bus. The controller circuits disposed in each of the cache memory devices compares the unique identification number with the predefined address bits, such that if the identification number and the predefined address bits match, the controller circuit provides control signals to enable its cache memory to execute the memory operation requested by the CPU at the cache memory location corresponding to the main memory address. In the event the identification does not match the predefined bits of the address, the memory controller circuit does not provide control signals to enable the memory to execute the memory operation and disables output driver circuits disposed within the cache.
摘要翻译：本发明包括耦合到总线的中央处理单元（CPU）。缓存存储器件耦合到总线以从CPU接收存储器请求。每个高速缓冲存储器件包括耦合到控制器电路的高速缓冲存储器。控制器电路提供控制信号，使得高速缓冲存储器能够执行由CPU请求的存储器操作。控制器电路被耦合以接收包括由CPU发出的存储器地址和存储器请求的预定义的地址位。设置在每个高速缓冲存储器设备中的每个控制器电路还被耦合以接收与耦合到总线的每个高速缓冲存储器设备唯一的识别号码。布置在每个高速缓冲存储器设备中的控制器电路将唯一标识号与预定义的地址位进行比较，使得如果标识号和预定义的地址位匹配，则控制器电路提供控制信号以使其高速缓冲存储器能够执行存储器 CPU在与主存储器地址相对应的缓存存储器位置处请求的操作。在识别与地址的预定义比特不匹配的情况下，存储器控制器电路不提供控制信号以使得存储器能够执行存储器操作并且禁用设置在高速缓存内的输出驱动器电路。

8. 发明授权

US5528541A Charge shared precharge scheme to reduce compare output delays 失效
标题翻译：充电共享预充电方案，以减少比较输出延迟
公开(公告)号：US5528541A
公开(公告)日：1996-06-18
申请号：US336524
申请日：1994-11-09
申请人： Atul V. Ghia , Pradip Banerjee , Patrick Chuang
发明人： Atul V. Ghia , Pradip Banerjee , Patrick Chuang
IPC分类号： G06F12/08 , G11C15/00 , H03K19/017 , G11C7/00
CPC分类号： G11C15/00 , H03K19/01728 , G06F12/0895
摘要： The charge shared precharge circuit of the present invention is coupled to the match line. The precharge circuit is disposed between the match line and a match line, and includes a CMOS passgate having an N channel and a P channel gate. An inverter acts as a match driver and is coupled between the match and match lines at the CMOS passgate's input and output. The input to the N channel gate of the pass gate is coupled through an inverter to the input of the P channel gate. The N channel gate is further coupled to V.sub.cc through two serially coupled P channel transistors receive BEQ line and an SAE signal, respectively. At the beginning of a compare cycle, BEQ is driven low as is SAE, thereby turning on the serially coupled P channel transistors and coupling V.sub.cc to the input of the N channel gate of the passgate. The P channel gate of the passgate is also opened due to the placement of the inverter between the N and P channel gates. The passgate is thereby turned on and current passes through the passgate between the match and match lines. The opening of the passgate and the coupling of the inverter between the match and match lines, results in a shorting of V.sub.cc to ground. The shorting of V.sub.cc to ground results in a voltage precharge of the match line to V.sub.cc /2. After a predetermined precharge time, the SAE signal is driven high thereby turning off the P channel transistor, and electrically decoupling V.sub.cc from the gates of the CMOS passgate and the match line. The compare circuit of the present invention then compares the bits of word A with word B, as described herein.
摘要翻译：本发明的电荷共享预充电电路耦合到匹配线。预充电电路设置在匹配线和匹配线之间，并且包括具有N沟道和P沟道栅极的CMOS通道。反相器作为匹配驱动器，并连接在CMOS通道门的输入和输出端的匹配线和匹配线之间。通过栅极的N沟道栅极的输入通过反相器耦合到P沟道栅极的输入端。 N沟道栅极进一步通过两个串联耦合的P沟道晶体管耦合到Vcc，所述P沟道晶体管分别接收BEQ线和SAE信号。在比较周期开始时，BEQ被驱动为低电平，如SAE，从而导通串联的P沟道晶体管，并将Vcc耦合到通孔的N沟道栅极的输入端。由于反相器在N沟道栅极和P沟道栅极之间的放置，所以通路的P沟道栅极也被打开。因此，通路被打开，电流在匹配线和匹配线之间通过通孔。通道的开启和反相器在匹配线和匹配线之间的耦合导致Vcc短路到地。将Vcc短路到地使得匹配线的电压预充电为Vcc / 2。在预定的预充电时间之后，SAE信号被驱动为高电平，从而截止P沟道晶体管，并且将电压从CMOS通道和匹配线的栅极去耦合Vcc。本发明的比较电路然后将字A与字B的位进行比较，如本文所述。

9. 发明授权

US07093051B2 Dynamic input/output: configurable data bus for optimizing data throughput 有权
公开(公告)号：US07093051B2
公开(公告)日：2006-08-15
申请号：US10246048
申请日：2002-09-17
申请人： Robert Haig , Pradip Banerjee
发明人： Robert Haig , Pradip Banerjee
IPC分类号： G06F13/14
CPC分类号： G06F13/161 , G06F13/1684
摘要： A dynamic I/O configuration and protocol includes a configurable data bus for optimizing data throughput. The configurable data bus includes multiple bi-directional data buses between a memory device and a controller to maximize the data transfer efficiency of operation sequences and thereby optimize data throughput to and from the memory device. Each of the bi-directional data buses are configured for utilization in both read operations from and write operations to the memory device. Using control input signal lines, the controller specifies a current operation to be performed and the data bus to be used to perform the current operation. The specific instructions that are provided from the controller to the memory device depend on the particular operation sequence being performed.

10. 发明授权

US5577228A Digital circuit for performing multicycle addressing in a digital memory 失效
标题翻译：用于在数字存储器中执行多周期寻址的数字电路
公开(公告)号：US5577228A
公开(公告)日：1996-11-19
申请号：US351900
申请日：1994-12-08
申请人： Pradip Banerjee , Atul V. Ghia , Simon Lau , Patrick Chuang
发明人： Pradip Banerjee , Atul V. Ghia , Simon Lau , Patrick Chuang
IPC分类号： G06F12/08 , G06F9/34
CPC分类号： G06F12/0893 , Y02B60/1225
摘要： The architecture of the cache memory of the present invention includes a data RAM, a TAG RAM, a controller and pad logic on a single integrated circuit chip. The cache memory is coupled to a CPU and a memory bus controller over a host bus. The host bus receives read data from the cache memory and provides write data to the cache memory. The cache memory controller provides signals to the memory bus controller to indicate whether data accessed by the CPU resides in the cache memory. The present invention increases memory speed by allowing circuit elements in the cache memory to operate during both phases of a system clock signal.
摘要翻译：本发明的高速缓冲存储器的结构在单个集成电路芯片上包括数据RAM，TAG RAM，控制器和焊盘逻辑。缓存存储器通过主机总线耦合到CPU和存储器总线控制器。主机总线从高速缓冲存储器接收读取数据，并向高速缓冲存储器提供写入数据。高速缓冲存储器控制器向存储器总线控制器提供信号以指示CPU访问的数据是否驻留在高速缓冲存储器中。本发明通过允许高速缓冲存储器中的电路元件在系统时钟信号的两个相位期间操作来提高存储器速度。

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