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1. 发明申请

US20140021616A1 SEMICONDUCTOR STRUCTURE 审中-公开
标题翻译：半导体结构
公开(公告)号：US20140021616A1
公开(公告)日：2014-01-23
申请号：US13553559
申请日：2012-07-19
申请人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
发明人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
IPC分类号： H01L23/532 , H01L23/58
CPC分类号： H01L23/585 , H01L23/562 , H01L25/0657 , H01L2224/04042 , H01L2224/05624 , H01L2225/06551 , H01L2225/06565
摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.
摘要翻译：提供半导体结构，并且包括具有边缘表面的基底和具有中心区域的器件表面，设置在器件表面上的裂纹阻挡结构以及包括设置在中心区域的器件表面上的部件的电路结构，并将电耦合到组件。互连构造成在桥接在裂纹停止结构上的同时从中心区域延伸到边缘表面。

2. 发明申请

US20140024146A1 SEMICONDUCTOR STRUCTURE 审中-公开
公开(公告)号：US20140024146A1
公开(公告)日：2014-01-23
申请号：US13565848
申请日：2012-08-03
申请人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
发明人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
IPC分类号： H01L21/768 , H01L21/50 , H01L21/66
CPC分类号： H01L23/585 , H01L23/562 , H01L25/0657 , H01L2224/04042 , H01L2224/05624 , H01L2225/06551 , H01L2225/06565
摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

3. 发明授权

US09093445B2 Packaging identical chips in a stacked structure 有权
标题翻译：在堆叠结构中包装相同的芯片
公开(公告)号：US09093445B2
公开(公告)日：2015-07-28
申请号：US13219084
申请日：2011-08-26
申请人： Evan G. Colgan , Luke D. LaCroix , Mark C. H. Lamorey , David B. Stone
发明人： Evan G. Colgan , Luke D. LaCroix , Mark C. H. Lamorey , David B. Stone
IPC分类号： H03K3/00 , H01L23/50 , H01L25/065 , G11C11/4072
CPC分类号： H01L23/50 , G11C11/4072 , H01L25/0657 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/0002 , H03K3/00 , H01L2924/00
摘要： Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.
摘要翻译：提供了用于在堆叠结构中包装相同处理的芯片的方法和结构。闩锁链包括与第一芯片相关联的具有单个或多个闩锁的第一闩锁链。第一锁存链被构造成从第一芯片读取数据信息。闩锁链包括具有与第二芯片相关联的单个或多个闩锁的第二闩锁链。第二锁存链被构造成从第二芯片读取数据信息。第一锁存链和第二锁存链彼此连接，使得形成跨越码片边界的单个锁存链。第一锁存链和第二锁存链被构造成分别提供用于识别第一芯片和第二芯片的识别信息。

4. 发明申请

US20130049834A1 PACKAGING IDENTICAL CHIPS IN A STACKED STRUCTURE 有权
标题翻译：在堆叠结构中包装标识牌
公开(公告)号：US20130049834A1
公开(公告)日：2013-02-28
申请号：US13219084
申请日：2011-08-26
申请人： Evan G. Colgan , Luke D. LaCroix , Mark C. H. Lamorey , David B. Stone
发明人： Evan G. Colgan , Luke D. LaCroix , Mark C. H. Lamorey , David B. Stone
IPC分类号： H03K3/00
CPC分类号： H01L23/50 , G11C11/4072 , H01L25/0657 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/0002 , H03K3/00 , H01L2924/00
摘要： Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.
摘要翻译：提供了用于在堆叠结构中包装相同处理的芯片的方法和结构。闩锁链包括与第一芯片相关联的具有单个或多个闩锁的第一闩锁链。第一锁存链被构造成从第一芯片读取数据信息。闩锁链包括具有与第二芯片相关联的单个或多个闩锁的第二闩锁链。第二锁存链被构造成从第二芯片读取数据信息。第一锁存链和第二锁存链彼此连接，使得形成跨越码片边界的单个锁存链。第一锁存链和第二锁存链被构造成分别提供用于识别第一芯片和第二芯片的识别信息。

5. 发明授权

US09006739B2 Semiconductor test and monitoring structure to detect boundaries of safe effective modulus 有权
公开(公告)号：US09006739B2
公开(公告)日：2015-04-14
申请号：US13448775
申请日：2012-04-17
申请人： James V. Crain, Jr. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
发明人： James V. Crain, Jr. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
IPC分类号： H01L21/66 , H01L23/522 , H01L23/00
CPC分类号： H01L22/34 , G01R31/2601 , G01R31/2607 , H01L23/522 , H01L24/13 , H01L24/14 , H01L2224/13111 , H01L2224/14131 , H01L2224/14515 , H01L2924/01029 , H01L2924/01047 , H01L2924/01051 , H01L2924/01082 , H01L2924/01083 , H01L2924/14
摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

6. 发明申请

US20130270558A1 SEMICONDUCTOR TEST AND MONITORING STRUCTURE TO DETECT BOUNDARIES OF SAFE EFFECTIVE MODULUS 有权
公开(公告)号：US20130270558A1
公开(公告)日：2013-10-17
申请号：US13448775
申请日：2012-04-17
申请人： James V. Crain, JR. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
发明人： James V. Crain, JR. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
IPC分类号： H01L23/498 , H01L21/66
CPC分类号： H01L22/34 , G01R31/2601 , G01R31/2607 , H01L23/522 , H01L24/13 , H01L24/14 , H01L2224/13111 , H01L2224/14131 , H01L2224/14515 , H01L2924/01029 , H01L2924/01047 , H01L2924/01051 , H01L2924/01082 , H01L2924/01083 , H01L2924/14
摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

7. 发明授权

US08796133B2 Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections 有权
标题翻译：在控制崩溃芯片连接下用于防止电介质裂纹的优化金属化
公开(公告)号：US08796133B2
公开(公告)日：2014-08-05
申请号：US13553941
申请日：2012-07-20
申请人： Griselda Bonilla , Timothy H. Daubenspeck , Mark C. H. Lamorey , Howard S. Landis , Xiao Hu Liu , David L. Questad , Thomas M. Shaw , David B. Stone
发明人： Griselda Bonilla , Timothy H. Daubenspeck , Mark C. H. Lamorey , Howard S. Landis , Xiao Hu Liu , David L. Questad , Thomas M. Shaw , David B. Stone
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L23/53295 , H01L23/3192 , H01L23/522 , H01L23/5329 , H01L2224/0401 , H01L2224/05 , H01L2224/05567 , H01L2224/05572 , H01L2224/13 , H01L2224/13021 , H01L2924/00014 , H01L2924/3512 , H01L2224/05552
摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.
摘要翻译：一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。衬底包括用于C4的多个附接垫。该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

8. 发明授权

US09245083B2 Method, structures and method of designing reduced delamination integrated circuits 有权
标题翻译：减少分层集成电路的设计方法，结构和方法
公开(公告)号：US09245083B2
公开(公告)日：2016-01-26
申请号：US13272395
申请日：2011-10-13
申请人： Mark C. H. Lamorey , David B. Stone
发明人： Mark C. H. Lamorey , David B. Stone
IPC分类号： H01L23/48 , G06F17/50 , H01L21/768 , H01L23/522
CPC分类号： G06F17/5077 , H01L21/76883 , H01L23/522 , H01L2224/11 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit wire structure. The structure includes a set of interconnect levels over a semiconductor substrate, each interconnect level of the set of interconnect levels comprising operational wires embedded in an interlevel dielectric layer; a dielectric barrier layer on an uppermost interconnect level of the set of interconnect levels and a bonding pad on the passivation layer; a stress reduction zone surrounding a perimeter of the bonding pad and extending into the set of interconnect levels; elongated fill wires in each of the interconnect levels in the stress reduction zone, the elongated fill wires not connected to any of the non-ground operational wires; and the elongated fill wires of each interconnect level of each set of interconnect levels physically connected to elongated fill wires of immediately upper and lower interconnect levels of the set of fill levels.
摘要翻译：集成电路线结构。该结构包括半导体衬底上的一组互连电平，该组互连电平的每个互连电平包括嵌入在层间电介质层中的操作线; 在所述一组互连级别的最上层互连层上的绝缘阻挡层和所述钝化层上的接合焊盘; 围绕所述焊盘的周边并延伸到所述一组互连级别的应力减小区; 在应力减小区域中的每个互连级别中的细长填充线，所述细长填充线不连接到任何非接地操作线; 并且每组互连级别的每个互连级别的细长填充线物理地连接到该组填充级别的立即上部和下部互连级别的细长填充线。

9. 发明授权

US07692954B2 Apparatus and method for integrating nonvolatile memory capability within SRAM devices 有权
标题翻译：在SRAM器件中集成非易失性存储器能力的装置和方法
公开(公告)号：US07692954B2
公开(公告)日：2010-04-06
申请号：US11684655
申请日：2007-03-12
申请人： Mark C. H. Lamorey
发明人： Mark C. H. Lamorey
IPC分类号： G11C11/00
CPC分类号： G11C14/0081 , G11C11/16
摘要： A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device.
摘要翻译：非易失性静态随机存取存储器（SRAM）器件包括一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，其配置为用于数据位的存储单元和一对耦合到存储单元。磁自旋转移装置被配置为在去除SRAM装置的电力之后将其存储在其中，并且还被配置为在向SRAM装置施加电力时利用保留的数据初始化存储单元。

10. 发明申请

US20090109735A1 DESIGN STRUCTURE FOR INITIALIZING REFERENCE CELLS OF A TOGGLE SWITCHED MRAM DEVICE 失效
标题翻译：用于初始化切换MRAM器件的参考电池的设计结构
公开(公告)号：US20090109735A1
公开(公告)日：2009-04-30
申请号：US11931492
申请日：2007-10-31
申请人： John K. DeBrosse , Mark C. H. Lamorey
发明人： John K. DeBrosse , Mark C. H. Lamorey
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/14 , G11C7/20 , G11C11/1673 , G11C27/02
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for initializing a reference cell in a toggle switched MRAM device, with a first sense amplifier configured for performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells; a first latch for storing the result of the first read operation; a second latch for storing the result of a second read operation by the first sense amplifier, wherein the second read operation is performed following the first read operation and the inversion of the value of one of the pair of the data cells; a third latch for storing the result of a third read operation by the first sense amplifier, wherein the third read operation is performed following the second read operation and the inversion of the value of the other of the pair of the data cells; and a majority compare device configured to compare of the results of the first, second and third operations respectively stored in the first, second and third latches, wherein an output of the majority compare operation is the initial state of the reference cell.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于在切换切换MRAM设备中初始化参考单元的设备，其中第一读出放大器被配置为通过比较通过所述参考单元的电流来执行参考单元的第一读取操作具有通过一对数据单元的平均电流的参考单元; 用于存储第一读取操作的结果的第一锁存器; 用于存储第一读出放大器的第二读取操作的结果的第二锁存器，其中在所述一对数据单元之一的所述第一读取操作和所述反转之后执行所述第二读取操作; 第三锁存器，用于存储第一读出放大器的第三读取操作的结果，其中在第二读取操作之后执行第三读取操作，并且反转一对数据单元中的另一个的值; 以及配置为比较分别存储在第一，第二和第三锁存器中的第一，第二和第三操作的结果的多数比较器件，其中多数比较操作的输出是参考单元的初始状态。

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