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1. 发明授权

US08796133B2 Optimization metallization for prevention of dielectric cracking under controlled collapse chip connections 有权
标题翻译：在控制崩溃芯片连接下用于防止电介质裂纹的优化金属化
公开(公告)号：US08796133B2
公开(公告)日：2014-08-05
申请号：US13553941
申请日：2012-07-20
申请人： Griselda Bonilla , Timothy H. Daubenspeck , Mark C. H. Lamorey , Howard S. Landis , Xiao Hu Liu , David L. Questad , Thomas M. Shaw , David B. Stone
发明人： Griselda Bonilla , Timothy H. Daubenspeck , Mark C. H. Lamorey , Howard S. Landis , Xiao Hu Liu , David L. Questad , Thomas M. Shaw , David B. Stone
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L23/53295 , H01L23/3192 , H01L23/522 , H01L23/5329 , H01L2224/0401 , H01L2224/05 , H01L2224/05567 , H01L2224/05572 , H01L2224/13 , H01L2224/13021 , H01L2924/00014 , H01L2924/3512 , H01L2224/05552
摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.
摘要翻译：一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。衬底包括用于C4的多个附接垫。该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

2. 发明申请

US20140021622A1 OPTIMIZATION METALLIZATION FOR PREVENTION OF DIELECTRIC CRACKING UNDER CONTROLLED COLLAPSE CHIP CONNECTIONS 有权
标题翻译：优化金属化防止电磁破碎在控制的胶片连接
公开(公告)号：US20140021622A1
公开(公告)日：2014-01-23
申请号：US13553941
申请日：2012-07-20
申请人： Griselda Bonilla , Timothy H. Daubenspeck , Mark C.H. Lamorey , Howard S. Landis , Xiao Hu Liu , David L. Questad , Thomas M. Shaw , David B. Stone
发明人： Griselda Bonilla , Timothy H. Daubenspeck , Mark C.H. Lamorey , Howard S. Landis , Xiao Hu Liu , David L. Questad , Thomas M. Shaw , David B. Stone
IPC分类号： H01L23/52 , H01L21/60
CPC分类号： H01L23/53295 , H01L23/3192 , H01L23/522 , H01L23/5329 , H01L2224/0401 , H01L2224/05 , H01L2224/05567 , H01L2224/05572 , H01L2224/13 , H01L2224/13021 , H01L2924/00014 , H01L2924/3512 , H01L2224/05552
摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.
摘要翻译：一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。衬底包括用于C4的多个附接垫。该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

3. 发明申请

US20080134111A1 REGIONAL PATTERN DENSITY DETERMINATION METHOD AND SYSTEM 有权
标题翻译：区域模式密度测定方法与系统
公开(公告)号：US20080134111A1
公开(公告)日：2008-06-05
申请号：US11566884
申请日：2006-12-05
申请人： Geoffrey K. Abbott , Howard S. Landis , David P. Parker
发明人： Geoffrey K. Abbott , Howard S. Landis , David P. Parker
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , G03F1/36 , H01L2924/0002 , H01L2924/00
摘要： A method and system of determining a localized measure of regional pattern density in a fabrication process of a chip are disclosed. In one embodiment, the method includes determining pattern density values for each cell of a plurality of cells of interest; averaging the pattern density values for each cell within a first selected region about a target cell to determine the localized measure of regional pattern density for the target cell; storing the localized measure of regional pattern density for the target cell; and repeating the averaging and the storing for each of the plurality of cells. The simplification of data allows for a localized measure of regional pattern density determination in much less time than conventional techniques.
摘要翻译：公开了一种在芯片的制造工艺中确定区域图案密度的局部度量的方法和系统。在一个实施例中，该方法包括确定感兴趣的多个细胞的每个细胞的图案密度值; 对围绕目标小区的第一选定区域内的每个小区的模式密度值进行平均，以确定目标小区的区域模式密度的局部测量; 存储目标细胞区域模式密度的局部测量; 并重复对所述多个单元中的每个单元进行平均和存储。数据的简化允许在比传统技术更少的时间内进行区域模式密度测定的局部测量。

4. 发明申请

US20070287200A1 VARIABLE OVERLAP OF DUMMY SHAPES FOR IMPROVED RAPID THERMAL ANNEAL UNIFORMITY 有权
标题翻译：改进的快速热稳定性的变形形状的可变叠加
公开(公告)号：US20070287200A1
公开(公告)日：2007-12-13
申请号：US11422622
申请日：2006-06-07
申请人： Brent A. Anderson , Howard S. Landis , Edward J. Nowak
发明人： Brent A. Anderson , Howard S. Landis , Edward J. Nowak
IPC分类号： H01L21/00
CPC分类号： H01L21/2686 , H01L21/76229 , H01L21/763
摘要： Embodiments of the invention provide a method, structure, service, etc. for variable overlap of dummy shapes for improved rapid thermal anneal uniformity. A method of providing uniform temperatures across a limited region of a wafer during a rapid thermal anneal process comprises determining a first reflectivity in a first portion of the limited region by measuring a density of first structures in the first portion. Next, the method determines a second reflectivity in a second portion of the limited region by measuring a density of second structures in the second portion. Specifically, the first structures comprise diffusion fill shapes and polysilicon conductor fill shapes (non-active dummy structures); and, the second structures comprise active circuit structures.
摘要翻译：本发明的实施例提供了用于改善快速热退火均匀性的虚拟形状的可变重叠的方法，结构，服务等。在快速热退火过程中在晶片的有限区域提供均匀温度的方法包括通过测量第一部分中的第一结构的密度来确定受限区域的第一部分中的第一反射率。接下来，该方法通过测量第二部分中的第二结构的密度来确定受限区域的第二部分中的第二反射率。具体地，第一结构包括扩散填充形状和多晶硅导体填充形状（非活性虚拟结构）; 并且第二结构包括有源电路结构。

5. 发明授权

US06992002B2 Shapes-based migration of aluminum designs to copper damascence 失效
标题翻译：基于形状的铝设计迁移到铜大马士革
公开(公告)号：US06992002B2
公开(公告)日：2006-01-31
申请号：US10305644
申请日：2002-11-26
申请人： Timothy G. Dunham , Ezra D. B. Hall , Howard S. Landis , Mark A. Lavin , William C. Leipold
发明人： Timothy G. Dunham , Ezra D. B. Hall , Howard S. Landis , Mark A. Lavin , William C. Leipold
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.
摘要翻译：一种在半导体器件中使用的互连结构，其通过在金属层中引入形状的空隙来互连多个不同的金属布线层，这些不同的金属布线层是连接的通孔。本发明还公开了一种构建这种结构的方法。

6. 发明授权

US5466636A Method of forming borderless contacts using a removable mandrel 失效
标题翻译：使用可移动心轴形成无边界触点的方法
公开(公告)号：US5466636A
公开(公告)日：1995-11-14
申请号：US946993
申请日：1992-09-17
申请人： John E. Cronin , Carter W. Kaanta , Donald M. Kenney , Michael L. Kerbaugh , Howard S. Landis , Brian J. Machesney , Paul Parries , Rosemary A. Previti-Kelly , John F. Rembetski
发明人： John E. Cronin , Carter W. Kaanta , Donald M. Kenney , Michael L. Kerbaugh , Howard S. Landis , Brian J. Machesney , Paul Parries , Rosemary A. Previti-Kelly , John F. Rembetski
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L29/417 , H01L21/44
CPC分类号： H01L27/10861 , H01L21/76838 , H01L21/76897 , H01L29/41766 , Y10S438/943
摘要： A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).
摘要翻译：一种用于使用可移除心轴（110）形成无边界触点（130,170,172）的半导体制造工艺。该方法包括将心轴沉积在设计成保护形成在基底（24）上的下面的结构（40）的下面的阻挡层（100）上。心轴由将以比阻挡层更快的速度蚀刻的材料制成，以允许心轴中的开口形成停止在阻挡层上而不穿透该层。在将形成在心轴中的第一开口（120）中的接触（130）沉积之后，形成第二开口（140），并且在其中沉积第二接触（170）。此后，移去心轴并用一层固体电介质材料（180）代替。

7. 发明授权

US08739078B2 Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications 有权
标题翻译：用于半导体应用的内置光学邻近校正的近似修整虚拟填充形状
公开(公告)号：US08739078B2
公开(公告)日：2014-05-27
申请号：US13353035
申请日：2012-01-18
申请人： Howard S. Landis
发明人： Howard S. Landis
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/36 , G03F1/44 , G03F7/70441 , G03F7/705 , G06F17/5068
摘要： Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes.
摘要翻译：提供了用于半导体应用的具有内置光学邻近校正（OPC）的虚拟填充形状的近邻修整。近邻修剪的方法包括将一个或多个孔形状添加到包括多个设计形状的半导体设计布局上。所述方法还包括修剪由所述一个或多个孔形状覆盖的所述多个中的相邻的一个。

8. 发明授权

US08423945B2 Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes 失效
标题翻译：满足半导体制造工艺技术密度要求的方法和系统
公开(公告)号：US08423945B2
公开(公告)日：2013-04-16
申请号：US12782337
申请日：2010-05-18
申请人： Jeanne P. Bickford , Allan O. Cruz , Michelle Gill , Howard S. Landis , David V. MacDonnell, II , Donald J. Samuels , Roger J. Yerdon
发明人： Jeanne P. Bickford , Allan O. Cruz , Michelle Gill , Howard S. Landis , David V. MacDonnell, II , Donald J. Samuels , Roger J. Yerdon
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die.
摘要翻译：提供了技术，系统和方法来优化用于集成电路的图案密度填充图案。该方法包括在保持模具的面积的同时调节划线的面积和调整的划线中的虚拟填充形状的密度，以实现与针对模具的特定设计的技术基础规则相关联的图案密度。

9. 发明授权

US08299775B2 Current-aligned auto-generated non-equiaxial hole shape for wiring 有权
标题翻译：电流对齐自动生成的非等轴孔形状用于接线
公开(公告)号：US08299775B2
公开(公告)日：2012-10-30
申请号：US11160428
申请日：2005-06-23
申请人： Howard S. Landis , David Parker , Jeanne-Tania Sucharitaves
发明人： Howard S. Landis , David Parker , Jeanne-Tania Sucharitaves
IPC分类号： G01R19/00
CPC分类号： H01L23/528 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method, system and program product for replacing isotropic hole shapes in a wiring layout with non-equiaxial hole shapes that are arranged in a direction of current flow, which increases current flow along the wire's longitudinal axis while decreasing current flow along the wire's transverse axis. One aspect of the invention includes a method including determining a direction of electrical current flow in a portion of a wiring layout; and placing at least one non-equiaxial hole shape within the portion of the wiring layout, wherein the non-equiaxial hole shape is arranged in the direction of electrical current flow. The invention accommodates the limitations of copper CMP within an automated tool without sacrificing the efficiency of a hand-tuned layout. The invention also includes a semiconductor device including at least one non-equiaxial hole shape.
摘要翻译：一种方法，系统和程序产品，用于在沿着电流流动方向布置的非等轴孔形状的布线布局中替换各向同性孔形状，其沿着线的纵向轴线增加电流，同时沿着线的横轴减小电流。本发明的一个方面包括一种方法，其包括确定布线布局的一部分中的电流流动的方向; 并且在所述布线布置部分内布置至少一个非等轴孔形状，其中所述非等轴孔形状沿电流流动方向布置。本发明在自动化工具中适应铜CMP的限制，而不牺牲手动布局的效率。本发明还包括包括至少一个非等轴孔形状的半导体器件。

10. 发明授权

US07930667B2 System and method of automated wire and via layout optimization description 有权
标题翻译：自动化线和布局优化描述的系统和方法
公开(公告)号：US07930667B2
公开(公告)日：2011-04-19
申请号：US11465473
申请日：2006-08-18
申请人： Bette L. Bergman Reuter , Howard S. Landis , Anthony K. Stamper , Jeanne-Tania Sucharitaves
发明人： Bette L. Bergman Reuter , Howard S. Landis , Anthony K. Stamper , Jeanne-Tania Sucharitaves
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5072
摘要： A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias.
摘要翻译：一种用于优化电路布局的系统和方法，更具体地，涉及一种用于优化电路布局并减少随机和系统电线以及经由开路和短路的布局布局数据准备的系统和方法。该方法包括在设计布局中剥离现有的通孔，并确定设计布局的设计参数，包括布线布局和尺寸。该方法还包括通过将通孔放置在远离布线和相邻通孔的边缘的情况下优化通孔布局。

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