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1. 发明授权

US09245083B2 Method, structures and method of designing reduced delamination integrated circuits 有权
标题翻译：减少分层集成电路的设计方法，结构和方法
公开(公告)号：US09245083B2
公开(公告)日：2016-01-26
申请号：US13272395
申请日：2011-10-13
申请人： Mark C. H. Lamorey , David B. Stone
发明人： Mark C. H. Lamorey , David B. Stone
IPC分类号： H01L23/48 , G06F17/50 , H01L21/768 , H01L23/522
CPC分类号： G06F17/5077 , H01L21/76883 , H01L23/522 , H01L2224/11 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit wire structure. The structure includes a set of interconnect levels over a semiconductor substrate, each interconnect level of the set of interconnect levels comprising operational wires embedded in an interlevel dielectric layer; a dielectric barrier layer on an uppermost interconnect level of the set of interconnect levels and a bonding pad on the passivation layer; a stress reduction zone surrounding a perimeter of the bonding pad and extending into the set of interconnect levels; elongated fill wires in each of the interconnect levels in the stress reduction zone, the elongated fill wires not connected to any of the non-ground operational wires; and the elongated fill wires of each interconnect level of each set of interconnect levels physically connected to elongated fill wires of immediately upper and lower interconnect levels of the set of fill levels.
摘要翻译：集成电路线结构。该结构包括半导体衬底上的一组互连电平，该组互连电平的每个互连电平包括嵌入在层间电介质层中的操作线; 在所述一组互连级别的最上层互连层上的绝缘阻挡层和所述钝化层上的接合焊盘; 围绕所述焊盘的周边并延伸到所述一组互连级别的应力减小区; 在应力减小区域中的每个互连级别中的细长填充线，所述细长填充线不连接到任何非接地操作线; 并且每组互连级别的每个互连级别的细长填充线物理地连接到该组填充级别的立即上部和下部互连级别的细长填充线。

2. 发明授权

US07692954B2 Apparatus and method for integrating nonvolatile memory capability within SRAM devices 有权
标题翻译：在SRAM器件中集成非易失性存储器能力的装置和方法
公开(公告)号：US07692954B2
公开(公告)日：2010-04-06
申请号：US11684655
申请日：2007-03-12
申请人： Mark C. H. Lamorey
发明人： Mark C. H. Lamorey
IPC分类号： G11C11/00
CPC分类号： G11C14/0081 , G11C11/16
摘要： A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device.
摘要翻译：非易失性静态随机存取存储器（SRAM）器件包括一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，其配置为用于数据位的存储单元和一对耦合到存储单元。磁自旋转移装置被配置为在去除SRAM装置的电力之后将其存储在其中，并且还被配置为在向SRAM装置施加电力时利用保留的数据初始化存储单元。

3. 发明申请

US20090109735A1 DESIGN STRUCTURE FOR INITIALIZING REFERENCE CELLS OF A TOGGLE SWITCHED MRAM DEVICE 失效
标题翻译：用于初始化切换MRAM器件的参考电池的设计结构
公开(公告)号：US20090109735A1
公开(公告)日：2009-04-30
申请号：US11931492
申请日：2007-10-31
申请人： John K. DeBrosse , Mark C. H. Lamorey
发明人： John K. DeBrosse , Mark C. H. Lamorey
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/14 , G11C7/20 , G11C11/1673 , G11C27/02
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for initializing a reference cell in a toggle switched MRAM device, with a first sense amplifier configured for performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells; a first latch for storing the result of the first read operation; a second latch for storing the result of a second read operation by the first sense amplifier, wherein the second read operation is performed following the first read operation and the inversion of the value of one of the pair of the data cells; a third latch for storing the result of a third read operation by the first sense amplifier, wherein the third read operation is performed following the second read operation and the inversion of the value of the other of the pair of the data cells; and a majority compare device configured to compare of the results of the first, second and third operations respectively stored in the first, second and third latches, wherein an output of the majority compare operation is the initial state of the reference cell.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于在切换切换MRAM设备中初始化参考单元的设备，其中第一读出放大器被配置为通过比较通过所述参考单元的电流来执行参考单元的第一读取操作具有通过一对数据单元的平均电流的参考单元; 用于存储第一读取操作的结果的第一锁存器; 用于存储第一读出放大器的第二读取操作的结果的第二锁存器，其中在所述一对数据单元之一的所述第一读取操作和所述反转之后执行所述第二读取操作; 第三锁存器，用于存储第一读出放大器的第三读取操作的结果，其中在第二读取操作之后执行第三读取操作，并且反转一对数据单元中的另一个的值; 以及配置为比较分别存储在第一，第二和第三锁存器中的第一，第二和第三操作的结果的多数比较器件，其中多数比较操作的输出是参考单元的初始状态。

4. 发明申请

US20080225590A1 APPARATUS AND METHOD FOR INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES 有权
标题翻译：在SRAM器件中集成非易失性存储器容量的装置和方法
公开(公告)号：US20080225590A1
公开(公告)日：2008-09-18
申请号：US11684655
申请日：2007-03-12
申请人： Mark C. H. Lamorey
发明人： Mark C. H. Lamorey
IPC分类号： G11C16/04
CPC分类号： G11C14/0081 , G11C11/16
摘要： A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device.
摘要翻译：非易失性静态随机存取存储器（SRAM）器件包括一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，其配置为用于数据位的存储单元和一对耦合到存储单元。磁自旋转移装置被配置为在去除SRAM装置的电力之后将其存储在其中，并且还被配置为在向SRAM装置施加电力时利用保留的数据初始化存储单元。

5. 发明授权

US06943810B2 Layered article data verification 失效
标题翻译：分层文章数据验证
公开(公告)号：US06943810B2
公开(公告)日：2005-09-13
申请号：US09683712
申请日：2002-02-06
申请人： Mark C. H. Lamorey , Rick L. Mohler
发明人： Mark C. H. Lamorey , Rick L. Mohler
IPC分类号： G06F17/50 , G06T7/00 , G09G5/00
CPC分类号： G06T7/0004 , G06F17/5081 , G06T7/0002 , G06T2207/30136 , G06T2207/30148
摘要： A method, system and program product to verify a data preparation employed on a plurality of design layers that make up an article. An instruction algorithm representative of the data preparation is restated in terms of fundamental algorithms having corresponding graphical representations. The graphical representations can be combined to form a combination graphical representation that is used to determine whether the data preparation is correct. The invention can be used to verify correct data preparation of highly complex articles.
摘要翻译：一种用于验证构成物品的多个设计层上采用的数据准备的方法，系统和程序产品。代表数据准备的指令算法根据具有相应图形表示的基本算法进行了重述。图形表示可以组合以形成用于确定数据准备是否正确的组合图形表示。本发明可用于验证高度复杂物品的正确数据准备。

6. 发明授权

US09006739B2 Semiconductor test and monitoring structure to detect boundaries of safe effective modulus 有权
公开(公告)号：US09006739B2
公开(公告)日：2015-04-14
申请号：US13448775
申请日：2012-04-17
申请人： James V. Crain, Jr. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
发明人： James V. Crain, Jr. , Mark C. H. Lamorey , Christopher D. Muzzy , Thomas M. Shaw , David B. Stone
IPC分类号： H01L21/66 , H01L23/522 , H01L23/00
CPC分类号： H01L22/34 , G01R31/2601 , G01R31/2607 , H01L23/522 , H01L24/13 , H01L24/14 , H01L2224/13111 , H01L2224/14131 , H01L2224/14515 , H01L2924/01029 , H01L2924/01047 , H01L2924/01051 , H01L2924/01082 , H01L2924/01083 , H01L2924/14
摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

7. 发明授权

US07944734B2 Integrating nonvolatile memory capability within SRAM devices 有权
标题翻译：在SRAM器件中集成非易失性存储器能力
公开(公告)号：US07944734B2
公开(公告)日：2011-05-17
申请号：US12631900
申请日：2009-12-07
申请人： Mark C. H. Lamorey
发明人： Mark C. H. Lamorey
IPC分类号： G11C11/00
CPC分类号： G11C14/0081 , G11C11/16
摘要： A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device.
摘要翻译：非易失性静态随机存取存储器（SRAM）器件包括一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，其配置为用于数据位的存储单元和一对耦合到存储单元。磁自旋转移装置被配置为在去除SRAM装置的电力之后将其存储在其中，并且还被配置为在向SRAM装置施加电力时利用保留的数据初始化存储单元。

8. 发明申请

US20090219749A1 METHOD AND APPARATUS FOR IMPLEMENTING CONCURRENT MULTIPLE LEVEL SENSING OPERATION FOR RESISTIVE MEMORY DEVICES 失效
标题翻译：用于实现电阻式存储器件的并联多电平感测操作的方法和装置
公开(公告)号：US20090219749A1
公开(公告)日：2009-09-03
申请号：US12039990
申请日：2008-02-29
申请人： Mark C. H. Lamorey , Thomas M. Maffitt
发明人： Mark C. H. Lamorey , Thomas M. Maffitt
IPC分类号： G11C7/06 , G11C11/56
CPC分类号： G11C13/00 , G11C11/1673 , G11C11/56 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： An apparatus for sensing the data state of a multiple level, programmable resistive memory device includes an active clamping device connected to a data leg that is selectively coupled a programmable resistive memory element, the clamping device configured to clamp a fixed voltage, at a first node of the data leg, across the memory element, thereby establishing a fixed current sinking capability thereof; and a plurality of differential amplifiers, each of the differential amplifiers configured to compare a first voltage input, taken at a second node of the data leg, with a second voltage input; wherein the second voltage input for each differential amplifier comprises different reference voltages with respect to one another so as to enable each differential amplifier to detect a different resistance threshold, thereby determining a specific resistance state of the programmable resistive memory element.
摘要翻译：用于感测多级可编程电阻式存储器件的数据状态的装置包括连接到数据支路的有源钳位装置，该有源钳位装置选择性地耦合可编程电阻性存储器元件，钳位装置被配置为在第一节点处钳位固定电压跨越存储元件，从而建立其固定的电流吸收能力; 以及多个差分放大器，所述差分放大器中的每一个被配置为将在所述数据支路的第二节点处获取的第一电压输入与第二电压输入进行比较; 其中每个差分放大器的第二电压输入包括相对于彼此的不同的参考电压，以使得每个差分放大器能够检测不同的电阻阈值，从而确定可编程电阻式存储器元件的特定电阻状态。

9. 发明申请

US20080247218A1 DESIGN STRUCTURE FOR IMPLEMENTING IMPROVED WRITE PERFORMANCE FOR PCRAM DEVICES 审中-公开
标题翻译：用于实现改进的PCRAM设备的写性能的设计结构
公开(公告)号：US20080247218A1
公开(公告)日：2008-10-09
申请号：US11851036
申请日：2007-09-06
申请人： Mark C. H. Lamorey , Thomas Nirschl
发明人： Mark C. H. Lamorey , Thomas Nirschl
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A design structure embodied in a machine readable medium used in a design process includes a circuit for implementing a write operation for a programmable resistive random access memory array, the circuit including a current source coupled to a bit line associated with a programmable resistive memory element; a dummy path configured for selective coupling to the bit line prior to activation of a word line associated with the memory element, wherein the passage of current through the bit line and dummy path precharges the bit line; and control circuitry for decoupling the dummy path from the bit line and for activating the word line associated with the memory element upon achieving a desired operating point of bit line current and bit line voltage, so as to cause current from the bit line to flow for a period of time selected to program the memory element to one of a low resistance state and a high resistance state.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于实现可编程电阻随机存取存储器阵列的写入操作的电路，该电路包括耦合到与可编程电阻存储器元件相关联的位线的电流源; 虚拟路径被配置为在激活与存储器元件相关联的字线之前选择性地耦合到位线，其中电流通过位线和虚路径预先充电位线; 以及控制电路，用于将虚拟路径与位线去耦，并且在实现位线电流和位线电压的期望工作点时激活与存储元件相关联的字线，以便使来自位线的电流流过选择的时间段将存储元件编程为低电阻状态和高电阻状态之一。

10. 发明申请

US20080175043A1 METHOD AND APPARATUS FOR INITIALIZING REFERENCE CELLS OF A TOGGLE SWITCHED MRAM DEVICE 失效
标题翻译：用于初始化切换MRAM器件的参考电池的方法和装置
公开(公告)号：US20080175043A1
公开(公告)日：2008-07-24
申请号：US11624707
申请日：2007-01-19
申请人： John K. DeBrosse , Mark C. H. Lamorey
发明人： John K. DeBrosse , Mark C. H. Lamorey
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/14 , G11C11/16 , G11C2207/2254
摘要： A method of determining an initial state of a reference cell in a fabricated memory array includes performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells, and storing the result of the first read operation; inverting the value of one of the pair of the data cells; performing a second read operation of the reference cell, and storing the result of the second read operation; inverting the value of the other of the pair of the data cells; performing a third read operation of the reference cell, and storing the result of the third read operation. A majority compare operation of the results of the first, second and third operations is performed, wherein the result of the majority compare operation is the initial state of the reference cell.
摘要翻译：确定制造的存储器阵列中的参考单元的初始状态的方法包括通过将通过参考单元的电流与通过一对数据单元的平均电流进行比较来执行参考单元的第一读取操作，并且存储第一次读取操作; 反转一对数据单元之一的值; 执行参考单元的第二读取操作，并存储第二读取操作的结果; 反转一对数据单元中的另一个的值; 执行参考单元的第三读取操作，并存储第三读取操作的结果。执行第一，第二和第三操作的结果的多数比较操作，其中多数比较操作的结果是参考单元的初始状态。

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