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1. 发明申请

US20080209285A1 Method and Circuit for Measuring Operating and Leakage Current of Individual Blocks Within an Array of Test Circuit Blocks 失效
标题翻译：用于测量测试电路块阵列内各个块的工作和泄漏电流的方法和电路
公开(公告)号：US20080209285A1
公开(公告)日：2008-08-28
申请号：US11679346
申请日：2007-02-27
申请人： Dhruva J. Acharyya , Sani R. Nassif , Rahul M. Rao
发明人： Dhruva J. Acharyya , Sani R. Nassif , Rahul M. Rao
IPC分类号： G01R31/28
CPC分类号： G01R31/3004 , G01R31/025 , G01R31/3008 , G01R31/318575
摘要： A method and circuits for measuring operating and leakage current of individual blocks within an array of test circuit blocks provides measurement free of error due to leakage currents through non-selected circuit blocks, without requiring an independent test facility for each circuit block. The circuit includes a pair of power supply grids and selection circuits at each test circuit block to select between a test power grid and a “rest” power grid used to supply current to the non-selected circuits. The leakage currents through the non-selected circuits are thus sourced from the rest grid and error that would otherwise be introduced in the test grid current measurement is avoided. The test circuit blocks may be ring oscillators, and the measured current may be the operating and/or leakage current of the ring oscillator. The circuit blocks may also include individual devices for IV (current-voltage) characterization using an additional gate input grid.
摘要翻译：用于测量测试电路块阵列内的各个块的工作和漏电流的方法和电路提供了通过未选择的电路块的漏电流而无误差的测量，而不需要每个电路块的独立测试设施。电路包括一对电源网格和每个测试电路块上的选择电路，用于在测试电网和用于向未选择电路提供电流的“静止”电网之间进行选择。因此，通过非选择电路的泄漏电流源于剩余电网，避免了在测试电网电流测量中引入的误差。测试电路块可以是环形振荡器，并且所测量的电流可以是环形振荡器的工作和/或泄漏电流。电路块还可以包括用于使用附加栅极输入栅格的IV（电流 - 电压）表征的单独器件。

2. 发明授权

US07550987B2 Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks 失效
标题翻译：用于测量测试电路块阵列内各个块的工作和漏电流的方法和电路
公开(公告)号：US07550987B2
公开(公告)日：2009-06-23
申请号：US11679346
申请日：2007-02-27
申请人： Dhruva J. Acharyya , Sani R. Nassif , Rahul M. Rao
发明人： Dhruva J. Acharyya , Sani R. Nassif , Rahul M. Rao
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G01R31/025 , G01R31/3008 , G01R31/318575
摘要： A method and circuits for measuring operating and leakage current of individual blocks within an array of test circuit blocks provides measurement free of error due to leakage currents through non-selected circuit blocks, without requiring an independent test facility for each circuit block. The circuit includes a pair of power supply grids and selection circuits at each test circuit block to select between a test power grid and a “rest” power grid used to supply current to the non-selected circuits. The leakage currents through the non-selected circuits are thus sourced from the rest grid and error that would otherwise be introduced in the test grid current measurement is avoided. The test circuit blocks may be ring oscillators, and the measured current may be the operating and/or leakage current of the ring oscillator. The circuit blocks may also include individual devices for IV (current-voltage) characterization using an additional gate input grid.
摘要翻译：用于测量测试电路块阵列内的各个块的工作和漏电流的方法和电路提供了通过未选择的电路块的漏电流而无误差的测量，而不需要每个电路块的独立测试设施。电路包括一对电源网格和每个测试电路块上的选择电路，用于在测试电网和用于向未选择电路提供电流的“静止”电网之间进行选择。因此，通过非选择电路的泄漏电流源于剩余电网，避免了在测试电网电流测量中引入的误差。测试电路块可以是环形振荡器，并且所测量的电流可以是环形振荡器的工作和/或泄漏电流。电路块还可以包括用于使用附加栅极输入栅格的IV（电流 - 电压）表征的单独器件。

3. 发明授权

US09471732B2 Equivalent device statistical modeling for bitline leakage modeling 有权
公开(公告)号：US09471732B2
公开(公告)日：2016-10-18
申请号：US13616991
申请日：2012-09-14
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

4. 发明授权

US08799732B2 Methodology for correlated memory fail estimations 有权
标题翻译：相关内存失败估算方法
公开(公告)号：US08799732B2
公开(公告)日：2014-08-05
申请号：US13369633
申请日：2012-02-09
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G11C29/00 , G06F11/00 , G11C29/08 , G06F17/18
CPC分类号： G11C29/08 , G06F17/18 , G11C29/56008
摘要： Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.
摘要翻译：通过基于多个参数构建用于分组的存储器单元模型来估计具有不同存储单元组的存储器阵列的相关故障分布，使用快速统计分析建立存储器单元模型的故障条件，计算每个存储器的参数的失效边界基于其相应的故障条件的单元模型，构建以失败边界为特征的存储器阵列模型。使用分配给存储器单元和外围逻辑元件的参数的随机值来重复模拟存储器阵列模型的操作，以识别每个模拟操作的存储器单元故障。对于每个存储器阵列模型计算平均值和方差，然后可以通过选择表现出最佳均值和方差的分组来识别最佳架构，受任何其他电路要求（例如功率或面积）的限制。

5. 发明授权

US08676516B2 Test circuit for bias temperature instability recovery measurements 失效
标题翻译：用于偏置温度不稳定性恢复测量的测试电路
公开(公告)号：US08676516B2
公开(公告)日：2014-03-18
申请号：US13524208
申请日：2012-06-15
申请人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
发明人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
IPC分类号： G01L3/00
CPC分类号： G01R31/31725 , G01R31/2856
摘要： A method and test circuit provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.
摘要翻译：一种方法和测试电路提供测量，以准确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

6. 发明授权

US08640062B2 Rapid estimation of temperature rise in wires due to Joule heating 有权
标题翻译：快速估算由于焦耳加热引起的电线温升
公开(公告)号：US08640062B2
公开(公告)日：2014-01-28
申请号：US13157980
申请日：2011-06-10
申请人： Kanak B. Agarwal , Sani R. Nassif , Ronald D. Rose , Chenggang Xu
发明人： Kanak B. Agarwal , Sani R. Nassif , Ronald D. Rose , Chenggang Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5018
摘要： A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations.
摘要翻译：提供了一种用于快速估计由于焦耳加热引起的电线温升的机制。该机构可以快速，准确地估计由于自加热引起的导线温升。快速估计对于在全芯片级处理数百万网络很重要。该机制通过考虑沿着导线的纵向热流动并在同一水平的横向热耦合到另一条导线来模拟横向热流。横向热流可以对温升产生显着影响。该机制还通过考虑通孔和层间电介质（ILD）的热导率来模拟垂直热流到衬底和散热片。该机制有效地解决了热系统，以实现用于固定电迁移违规的物理设计优化（例如，线尺寸等）。

7. 发明申请

US20130212444A1 METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS 有权
标题翻译：相关记忆失败估算方法
公开(公告)号：US20130212444A1
公开(公告)日：2013-08-15
申请号：US13369633
申请日：2012-02-09
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/08 , G06F17/18 , G11C29/56008
摘要： Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.
摘要翻译：通过基于多个参数构建用于分组的存储器单元模型来估计具有不同存储单元组的存储器阵列的相关故障分布，使用快速统计分析建立存储器单元模型的故障条件，计算每个存储器的参数的失效边界基于其相应的故障条件的单元模型，构建以失败边界为特征的存储器阵列模型。使用分配给存储器单元和外围逻辑元件的参数的随机值来重复模拟存储器阵列模型的操作，以识别每个模拟操作的存储器单元故障。对于每个存储器阵列模型计算平均值和方差，然后可以通过选择表现出最佳均值和方差的分组来识别最佳架构，受任何其他电路要求（例如功率或面积）的限制。

8. 发明授权

US08365118B2 Broken-spheres methodology for improved failure probability analysis in multi-fail regions 有权
标题翻译：用于改善多故障区域故障概率分析的破碎球方法
公开(公告)号：US08365118B2
公开(公告)日：2013-01-29
申请号：US12477361
申请日：2009-06-03
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
IPC分类号： G06F9/455
CPC分类号： G06F11/008
摘要： A failure probability for a system having multi-fail regions is computed by generating failure directions in a space whose dimensions are the system parameters under consideration. The failure directions are preferably uniform, forming radial slices. The failure directions may be weighted. The radial slices have fail boundaries defining fail regions comparable to broken shells. The distribution of the system parameters is integrated across the broken shell regions to derive a failure contribution for each failure direction. The failure probability is the sum of products of each failure contribution and its weight. Failure contributions are computed using equivalent expressions dependent on the number of dimensions, which can be used to build lookup tables for normalized fail boundary radii. The entire process can be iteratively repeated with successively increasing failure directions until the failure probability converges. The method is particularly useful in analyzing failure probability of electrical circuits such as memory cells.
摘要翻译：通过在尺寸为所考虑的系统参数的空间中生成故障方向来计算具有多故障区域的系统的故障概率。故障方向优选均匀，形成径向切片。失败方向可能被加权。径向切片的失效边界定义与断裂壳相当的失效区域。系统参数的分布在破裂的外壳区域中集成，以导出每个故障方向的故障贡献。故障概率是每个失效贡献的乘积和其重量之和。使用等同表达式计算故障贡献，取决于维数，可用于构建归一化失效边界半径的查找表。可以连续增加故障方向，迭代重复整个过程，直到故障概率收敛。该方法在分析诸如存储器单元之类的电路的故障概率方面特别有用。

9. 发明申请

US20120319675A1 CALIBRATION OF NON-CONTACT VOLTAGE SENSORS 失效
标题翻译：非接触式电压传感器的校准
公开(公告)号：US20120319675A1
公开(公告)日：2012-12-20
申请号：US13159568
申请日：2011-06-14
申请人： Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller , Sani R. Nassif
发明人： Wael El-Essawy , Alexandre Peixoto Ferreira , Thomas Walter Keller , Sani R. Nassif
IPC分类号： G01R35/00 , G01R1/20
CPC分类号： G01R35/02 , G01R15/207
摘要： Calibration of a non-contact voltage sensor provides improved accuracy for measuring voltage on a conductor such as an AC branch circuit wire. In a calibration mode, a predetermined voltage is imposed on a first voltage sensing conductor integrated in the non-contact voltage sensor, while a voltage on a second voltage sensing conductor is measured using a circuit of predetermined input impedance. The capacitance between the wire and each of the voltage sensing conductors may be the same, so that in measurement mode, when the first and second voltage sensing conductors are coupled together, the effective series capacitance provided in combination with the predetermined input impedance is four times as great. The results of the voltage measurement made in the calibration mode can thereby be used to adjust subsequent voltage measurements made in measurement mode with the first and second voltage sensing conductors combined in parallel.
摘要翻译：非接触式电压传感器的校准为测量诸如AC分支电路线的导体上的电压提供了更高的精度。在校准模式中，在集成在非接触电压传感器中的第一电压感测导体上施加预定电压，同时使用预定输入阻抗的电路测量第二电压感测导体上的电压。导线与每个电压感测导体之间的电容可以相同，使得在测量模式下，当第一和第二电压感测导体耦合在一起时，与预定输入阻抗组合提供的有效串联电容是四倍一样好因此，在校准模式中进行的电压测量的结果可用于调节在测量模式下进行的随后的电压测量，其中第一和第二电压感测导体并联组合。

10. 发明申请

US20120317523A1 Reducing Through Process Delay Variation in Metal Wires 有权
标题翻译：通过金属线的过程延迟变化减少
公开(公告)号：US20120317523A1
公开(公告)日：2012-12-13
申请号：US13157909
申请日：2011-06-10
申请人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
发明人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A mechanism is provided for reducing through process delay variation in metal wires by layout retargeting. The mechanism performs initial retargeting, decomposition, and resolution enhancement techniques. For example, the mechanism may perform optical proximity correction. The mechanism then performs lithographic simulation and optical rules checking. The mechanism provides retargeting rules developed based on coupling lithography simulation and resistance/capacitance (RC) extraction. The mechanism performs RC extraction to capture non-linear dependency of RC on design shape dimensions. If the electrical properties in the lithographic simulation are within predefined specifications, the mechanism accepts the retargeting rules; however, if the electrical properties from RC extraction are outside the predefined specifications, the mechanism modifies the retargeting rules and repeats resolution enhancement techniques.
摘要翻译：提供了一种通过布局重新定位来减少金属线中的工艺延迟变化的机制。该机制执行初始重定向，分解和分辨率增强技术。例如，该机构可以执行光学邻近校正。该机制进行光刻模拟和光学规则检查。该机制提供了基于耦合光刻模拟和电阻/电容（RC）提取开发的重定向规则。该机制执行RC提取以捕获RC对设计形状尺寸的非线性依赖性。如果光刻仿真中的电性能在预定义的规格范围内，则该机制接受重定向规则; 然而，如果来自RC提取的电性能超出预定义的规范，则该机制修改重定向规则并重复分辨率增强技术。

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