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1. 发明授权

US08365118B2 Broken-spheres methodology for improved failure probability analysis in multi-fail regions 有权
标题翻译：用于改善多故障区域故障概率分析的破碎球方法
公开(公告)号：US08365118B2
公开(公告)日：2013-01-29
申请号：US12477361
申请日：2009-06-03
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
IPC分类号： G06F9/455
CPC分类号： G06F11/008
摘要： A failure probability for a system having multi-fail regions is computed by generating failure directions in a space whose dimensions are the system parameters under consideration. The failure directions are preferably uniform, forming radial slices. The failure directions may be weighted. The radial slices have fail boundaries defining fail regions comparable to broken shells. The distribution of the system parameters is integrated across the broken shell regions to derive a failure contribution for each failure direction. The failure probability is the sum of products of each failure contribution and its weight. Failure contributions are computed using equivalent expressions dependent on the number of dimensions, which can be used to build lookup tables for normalized fail boundary radii. The entire process can be iteratively repeated with successively increasing failure directions until the failure probability converges. The method is particularly useful in analyzing failure probability of electrical circuits such as memory cells.
摘要翻译：通过在尺寸为所考虑的系统参数的空间中生成故障方向来计算具有多故障区域的系统的故障概率。故障方向优选均匀，形成径向切片。失败方向可能被加权。径向切片的失效边界定义与断裂壳相当的失效区域。系统参数的分布在破裂的外壳区域中集成，以导出每个故障方向的故障贡献。故障概率是每个失效贡献的乘积和其重量之和。使用等同表达式计算故障贡献，取决于维数，可用于构建归一化失效边界半径的查找表。可以连续增加故障方向，迭代重复整个过程，直到故障概率收敛。该方法在分析诸如存储器单元之类的电路的故障概率方面特别有用。

2. 发明申请

US20100313070A1 BROKEN-SPHERES METHODOLOGY FOR IMPROVED FAILURE PROBABILITY ANALYSIS IN MULTI-FAIL REGIONS 有权
标题翻译：改进的多故障区域故障概率分析方法
公开(公告)号：US20100313070A1
公开(公告)日：2010-12-09
申请号：US12477361
申请日：2009-06-03
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Zhuo Li , Sani R. Nassif
IPC分类号： G06F11/26
CPC分类号： G06F11/008
摘要： A failure probability for a system having multi-fail regions is computed by generating failure directions in a space whose dimensions are the system parameters under consideration. The failure directions are preferably uniform, forming radial slices. The failure directions may be weighted. The radial slices have fail boundaries defining fail regions comparable to broken shells. The distribution of the system parameters is integrated across the broken shell regions to derive a failure contribution for each failure direction. The failure probability is the sum of products of each failure contribution and its weight. Failure contributions are computed using equivalent expressions dependent on the number of dimensions, which can be used to build lookup tables for normalized fail boundary radii. The entire process can be iteratively repeated with successively increasing failure directions until the failure probability converges. The method is particularly useful in analyzing failure probability of electrical circuits such as memory cells.
摘要翻译：通过在尺寸为所考虑的系统参数的空间中生成故障方向来计算具有多故障区域的系统的故障概率。故障方向优选均匀，形成径向切片。失败方向可能被加权。径向切片的失效边界定义与断裂壳相当的失效区域。系统参数的分布在破裂的外壳区域中集成，以导出每个故障方向的故障贡献。故障概率是每个失效贡献的乘积和其重量之和。使用等同表达式计算故障贡献，取决于维数，可用于构建归一化失效边界半径的查找表。可以连续增加故障方向，迭代重复整个过程，直到故障概率收敛。该方法在分析诸如存储器单元之类的电路的故障概率方面特别有用。

3. 发明授权

US08214777B2 On-chip leakage current modeling and measurement circuit 有权
标题翻译：片内漏电流建模与测量电路
公开(公告)号：US08214777B2
公开(公告)日：2012-07-03
申请号：US12419377
申请日：2009-04-07
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G01R31/025 , G11C29/006 , G11C29/028 , G11C29/50 , G11C2029/5006 , G11C2029/5602
摘要： A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.
摘要翻译：泄漏电流监测电路在集成在管芯上的数字电路中提供精确的统计代表性的真实截止漏电流的模拟。与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流，类型设备已超过阈值。测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。

4. 发明申请

US20090132873A1 Method and System for Determining Element Voltage Selection Control Values for a Storage Device 失效
标题翻译：用于确定存储设备的元件电压选择控制值的方法和系统
公开(公告)号：US20090132873A1
公开(公告)日：2009-05-21
申请号：US11941161
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C29/00
CPC分类号： G11C29/006 , G11C11/41 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/72
摘要： A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization.
摘要翻译：用于确定存储设备的元件电压选择控制值的方法和系统在保持特定性能水平的同时在存储阵列中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。在测试时间，除非要求该元件满足性能要求，否则需要为虚拟电源轨设置最小电源电压的每个元件的选择电路确定数字控制值。然后可以将该组数字控制值编程为保险丝，或者用于在制造时调整掩模，或者随着存储设备一起提供在介质上，并在系统初始化时将其加载到设备中。

5. 发明申请

US20120293197A1 On-Chip Leakage Current Modeling and Measurement Circuit 失效
标题翻译：片内泄漏电流建模与测量电路
公开(公告)号：US20120293197A1
公开(公告)日：2012-11-22
申请号：US13484868
申请日：2012-05-31
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
IPC分类号： G01R31/26 , G06F17/50
CPC分类号： G01R31/025 , G11C29/006 , G11C29/028 , G11C29/50 , G11C2029/5006 , G11C2029/5602
摘要： At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.
摘要翻译：与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流，类型设备已超过阈值。测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。

6. 发明授权

US08214190B2 Methodology for correlated memory fail estimations 有权
标题翻译：相关内存失败估算方法
公开(公告)号：US08214190B2
公开(公告)日：2012-07-03
申请号：US12422420
申请日：2009-04-13
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/504 , G06F2217/10
摘要： Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.
摘要翻译：通过基于多个参数构建用于分组的存储器单元模型来估计具有不同存储单元组的存储器阵列的相关故障分布，使用快速统计分析建立存储器单元模型的故障条件，计算每个存储器的参数的失效边界基于其相应的故障条件的单元模型，构建以失败边界为特征的存储器阵列模型。使用分配给存储器单元和外围逻辑元件的参数的随机值来重复模拟存储器阵列模型的操作，以识别每个模拟操作的存储器单元故障。对于每个存储器阵列模型计算平均值和方差，然后可以通过选择表现出最佳均值和方差的分组来识别最佳架构，受任何其他电路要求（例如功率或面积）的限制。

7. 发明授权

US08208339B2 Computer program product for controlling a storage device having per-element selectable power supply voltages 有权
标题翻译：用于控制具有每元件可选电源电压的存储装置的计算机程序产品
公开(公告)号：US08208339B2
公开(公告)日：2012-06-26
申请号：US13115149
申请日：2011-05-25
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： A computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元件可选择的电源电压来控制存储设备的计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

8. 发明授权

US07733720B2 Method and system for determining element voltage selection control values for a storage device 失效
标题翻译：用于确定存储设备的元件电压选择控制值的方法和系统
公开(公告)号：US07733720B2
公开(公告)日：2010-06-08
申请号：US11941161
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C29/00
CPC分类号： G11C29/006 , G11C11/41 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/72
摘要： A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization.
摘要翻译：用于确定存储设备的元件电压选择控制值的方法和系统在保持特定性能水平的同时在存储阵列中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。在测试时间，除非要求该元件满足性能要求，否则需要为虚拟电源轨设置最小电源电压的每个元件的选择电路确定数字控制值。然后可以将该组数字控制值编程为保险丝或用于在制造时调整掩模，或者与存储设备一起提供在介质上并在系统初始化时加载到设备中。

9. 发明申请

US20090172451A1 METHOD AND COMPUTER PROGRAM FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 有权
标题翻译：用于控制具有全元选择电源电压的存储设备的方法和计算机程序
公开(公告)号：US20090172451A1
公开(公告)日：2009-07-02
申请号：US12399551
申请日：2009-03-06
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G06F1/32
CPC分类号： G11C11/417 , G11C5/14
摘要： A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元素可选择的电源电压来控制存储设备的方法和计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非该元件需要较高的电源电压以满足性能要求。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

10. 发明申请

US20130014069A1 Equivalent Device Statistical Modeling for Bitline Leakage Modeling 有权
标题翻译：用于位线泄漏建模的等效装置统计建模
公开(公告)号：US20130014069A1
公开(公告)日：2013-01-10
申请号：US13616991
申请日：2012-09-14
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.
摘要翻译：提供了用于将集成电路设计的多个装置建模为单个统计上等同的宽装置的机构。分析集成电路设计以识别具有多个装置的集成电路设计的一部分。对于多个装置，产生统计模型的单个统计学上等效的宽装置，该统计模型具有捕获多个装置中的各个装置的统计工作特性分布的单个统计学等效的宽装置的至少一个操作特性的统计分布。单个统计学等效的宽设备的至少一个统计工作特性是各个设备的统计操作特性的复杂非线性函数。集成电路设计采用单一统计学上等效的宽设备进行建模。

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