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1. 发明授权

US09087739B2 Pattern improvement in multiprocess patterning 有权
标题翻译：多进程图案化模式的改进
公开(公告)号：US09087739B2
公开(公告)日：2015-07-21
申请号：US12581422
申请日：2009-10-19
申请人： Derren N. Dunn , Ioana Graur , Scott M. Mansfield
发明人： Derren N. Dunn , Ioana Graur , Scott M. Mansfield
IPC分类号： G06F17/50 , H01L21/66 , G03F7/20 , H01L21/033 , H01L21/311 , H01L21/768
CPC分类号： H01L22/12 , G03F1/36 , G03F1/80 , G03F7/70441 , G03F7/705 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816
摘要： Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.
摘要翻译：通过在材料，反应物，特征尺寸，特征密度，工艺参数等方面对材料去除和沉积过程进行建模，以及这些参数对这些参数的影响，可以实现对最终生产的半导体结构中的集成电路图案设计的改进的保真度由于微加载和RIE滞后（包括反RIE滞后）导致的蚀刻和材料沉积偏差，并且使用模型通过包括硬掩模图案分解在内的预期制造方法步骤向后工作，以形态地开发用于大多数或所有工艺步骤的特征图案这将在整个过程完成时产生期望的特征尺寸和形状。可以通过使用工艺辅助特征来局部地调整材料沉积和去除速率来简化工艺的建模。

2. 发明申请

US20110091815A1 Pattern Improvement in Multiprocess Patterning 有权
标题翻译：多进程模式的模式改进
公开(公告)号：US20110091815A1
公开(公告)日：2011-04-21
申请号：US12581422
申请日：2009-10-19
申请人： Derren N. Dunn , Ioana Graur , Scott M. Mansfield
发明人： Derren N. Dunn , Ioana Graur , Scott M. Mansfield
IPC分类号： G03F7/20
CPC分类号： H01L22/12 , G03F1/36 , G03F1/80 , G03F7/70441 , G03F7/705 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816
摘要： Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.
摘要翻译：通过在材料，反应物，特征尺寸，特征密度，工艺参数等方面对材料去除和沉积过程进行建模，以及这些参数对这些参数的影响，可以实现对最终生产的半导体结构中的集成电路图案设计的改进的保真度由于微加载和RIE滞后（包括反RIE滞后）导致的蚀刻和材料沉积偏差，并且使用模型通过包括硬掩模图案分解在内的预期制造方法步骤向后工作，以形态地开发用于大多数或所有工艺步骤的特征图案这将在整个过程完成时产生期望的特征尺寸和形状。可以通过使用工艺辅助特征来局部地调整材料沉积和去除速率来简化工艺的建模。

3. 发明授权

US07102232B2 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US07102232B2
公开(公告)日：2006-09-05
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

4. 发明申请

US20100042967A1 MEEF REDUCTION BY ELONGATION OF SQUARE SHAPES 有权
标题翻译：通过平面形状的缩小来减少MEEF
公开(公告)号：US20100042967A1
公开(公告)日：2010-02-18
申请号：US12191493
申请日：2008-08-14
申请人： Derren N. Dunn , Michael M. Crouse , Henning Haffner , Michael E. Scaman
发明人： Derren N. Dunn , Michael M. Crouse , Henning Haffner , Michael E. Scaman
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method that purposely relaxes OPC algorithm constraints to allow post OPC mask shapes to elongate along one direction (particularly lowering the 1-dimensional MEEF in this direction with the result of an effectively overall lowered MEEF) to produce a pattern on wafer that is circular to within an acceptable tolerance.
摘要翻译：一种意图放松OPC算法约束以允许OPC掩模形状沿着一个方向伸长的方法（特别是在该方向上降低1维MEEF，结果是有效地降低了MEEF），从而在晶圆上产生一个圆形到在可接受的容限内。

5. 发明申请

US20090191468A1 Contact Level Mask Layouts By Introducing Anisotropic Sub-Resolution Assist Features 审中-公开
标题翻译：通过引入各向异性分解辅助功能的接触层面罩布局
公开(公告)号：US20090191468A1
公开(公告)日：2009-07-30
申请号：US12021527
申请日：2008-01-29
申请人： Michael M. Crouse , Derren N. Dunn , Henning Haffner , Michael E. Scaman
发明人： Michael M. Crouse , Derren N. Dunn , Henning Haffner , Michael E. Scaman
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： This disclosure includes a SRAF layout that minimizes the number of SRAFs required to reliably print contact shapes. A method is provided that reduces the number of necessary SRAF features on a mask, placing at least two elongated SRAF shapes on the mask such that the elongated SRAF shapes extend past at least one edge of a mask shape in at least one direction.
摘要翻译：本公开包括SRAF布局，其最小化可靠地打印接触形状所需的SRAF的数量。提供了一种减少掩模上必要的SRAF特征的数量的方法，在掩模上放置至少两个细长的SRAF形状，使得细长SRAF形状延伸经过至少一个方向上的掩模形状的至少一个边缘。

6. 发明授权

US07402532B2 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US07402532B2
公开(公告)日：2008-07-22
申请号：US11499220
申请日：2006-08-04
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

7. 发明授权

US07211507B2 PE-ALD of TaN diffusion barrier region on low-k materials 有权
标题翻译：低k材料的TaN扩散阻挡区的PE-ALD
公开(公告)号：US07211507B2
公开(公告)日：2007-05-01
申请号：US10709865
申请日：2004-06-02
申请人： Derren N. Dunn , Hyungjun Kim , Stephen M. Rossnagel , Soon-Cheon Seo
发明人： Derren N. Dunn , Hyungjun Kim , Stephen M. Rossnagel , Soon-Cheon Seo
IPC分类号： H01L21/285
CPC分类号： H01L21/76846 , H01L21/28562 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Methods of depositing a tantalum-nitride (TaN) diffusion barrier region on low-k materials. The methods include forming a protective layer on the low-k material substrate by performing plasma-enhanced atomic layer deposition (PE-ALD) from tantalum-based precursor and a nitrogen plasma in a chamber. The protective layer has a nitrogen content greater than its tantalum content. A substantially stoichiometric tantalum-nitride layer is then formed by performing PE-ALD from the tantalum-based precursor and a plasma including hydrogen and nitrogen. The invention also includes the tantalum-nitride diffusion barrier region so formed. In one embodiment, the metal precursor includes tantalum penta-chloride (TaCl5). The invention generates a sharp interface between low-k materials and liner materials.
摘要翻译：在低k材料上沉积氮化钽（TaN）扩散阻挡区域的方法。所述方法包括通过从钽基前体和室中的氮等离子体进行等离子体增强原子层沉积（PE-ALD）在低k材料衬底上形成保护层。保护层的氮含量大于其钽含量。然后通过从钽基前体和包括氢和氮的等离子体中进行PE-ALD形成基本上化学计量的氮化钽层。本发明还包括如此形成的氮化钽 - 氮化物扩散阻挡区域。在一个实施方案中，金属前体包括五氯化钽（TaCl 5 N 5）。本发明在低k材料和衬垫材料之间产生尖锐的界面。

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