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1. 发明授权

US08860141B2 Layout to minimize FET variation in small dimension photolithography 有权
标题翻译：布局以最小化小尺度光刻中的FET变化
公开(公告)号：US08860141B2
公开(公告)日：2014-10-14
申请号：US13345439
申请日：2012-01-06
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
IPC分类号： H01L21/70
CPC分类号： H01L27/1104 , G11C5/025 , H01L21/28123 , H01L27/0207
摘要： A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.
摘要翻译：半导体芯片具有在足够小以至要求第一掩模和第二掩模的特定等级上的形状，第一掩模和第二掩模在处理期间分开曝光中使用。半导体芯片上的电路需要在第一和第二FET（场效应晶体管）之间的紧密跟踪。例如，特定级别可以是门形状级别。使用第一掩模和第二掩模的栅极形状的单独曝光将导致比仅由第一掩模限定的栅极形状的FET更差的FET跟踪（例如，栅极长度，阈值电压）。通过布置电路来选择性地提高FET跟踪，使得选择性FET由第一掩模限定。特别地，静态随机存取存储器（SRAM）设计受益于在SRAM单元中紧密跟踪六个或更多个FET。

2. 发明申请

US20120087176A1 DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP 有权
标题翻译：动态随机存取存储器的数据安全使用身体偏差清除数据上电
公开(公告)号：US20120087176A1
公开(公告)日：2012-04-12
申请号：US12898924
申请日：2010-10-06
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
IPC分类号： G11C11/24 , G11C7/00
CPC分类号： G11C7/24 , G11C5/145 , G11C7/20 , G11C11/4072 , G11C11/4078
摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.
摘要翻译：电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。通过增加单元的体电压同时接通DRAM存储单元的晶体管，可以擦除所有的DRAM存储单元。在示例电路中，通过由对存储器单元的p阱施加电压的上电复位（POR）信号控制的电荷泵增加体电压。向p阱施加的电压降低了电池的阈值电压，使得存储器单元的NFET晶体管将导通。当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。

3. 发明申请

US20100214859A1 Implementing Boosted Wordline Voltage in Memories 有权
标题翻译：在记忆中实现增强的字线电压
公开(公告)号：US20100214859A1
公开(公告)日：2010-08-26
申请号：US12389420
申请日：2009-02-20
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00 , G11C8/08 , G11C5/14
CPC分类号： G11C11/413 , G11C8/08
摘要： A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.
摘要翻译：一种用于在存储器中实现升压的字线电压的方法和字线电压升压电路，以及设置有该电路所在的设计结构。字线升压电路接收预充电信号，使用耦合到自举电容器的开关晶体管，并响应于预充电信号产生升压电压电平。提升的电压电平被施加到字线驱动器的输出级的电压源，导致所选字线的字线电压电平升高。开关晶体管由预充电信号控制，并且提供升压电压电平的自举电容的节点由开关晶体管驱动为高电平。

4. 发明授权

US08467230B2 Data security for dynamic random access memory using body bias to clear data at power-up 有权
标题翻译：使用身体偏倚的动态随机存取存储器的数据安全性，以在上电时清除数据
公开(公告)号：US08467230B2
公开(公告)日：2013-06-18
申请号：US12898924
申请日：2010-10-06
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
IPC分类号： G11C11/24
CPC分类号： G11C7/24 , G11C5/145 , G11C7/20 , G11C11/4072 , G11C11/4078
摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.
摘要翻译：电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。通过增加单元的体电压同时接通DRAM存储单元的晶体管，可以擦除所有的DRAM存储单元。在示例电路中，通过由对存储器单元的p阱施加电压的上电复位（POR）信号控制的电荷泵增加体电压。向p阱施加的电压降低了电池的阈值电压，使得存储器单元的NFET晶体管将导通。当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。

5. 发明授权

US08159260B1 Delay chain burn-in for increased repeatability of physically unclonable functions 失效
标题翻译：延迟链老化可增加物理不可克隆功能的重复性
公开(公告)号：US08159260B1
公开(公告)日：2012-04-17
申请号：US12898044
申请日：2010-10-05
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： H03K19/00 , G06F11/30 , G06F13/00
CPC分类号： G06F7/588 , H04L9/0866
摘要： A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
摘要翻译：电路和方法通过在芯片烧录期间通过两个延迟链增强信号延迟的变化来增加物理上不可检测的功能（PUF）的重复性。老化电路在老化过程中将两个延迟链的输入保持相反的随机值。延迟链中所有在输入端具有低电平值的PFET将以更高的导通电压进行烧录。由于在两个延迟链中受影响的PFET在老化期间被相反的转变驱动，所以两个延迟链中的延迟组件的交替组合受老化周期的影响。在正常操作下，两个延迟链看到相同的输入，所以只有一个链延迟增加，以实现两个延迟路径的统计上可靠的差异，从而增加了PUF电路的整体重复性。

6. 发明申请

US20120081143A1 DELAY CHAIN BURN-IN FOR INCREASED REPEATABILITY OF PHYSICALLY UNCLONABLE FUNCTIONS 失效
标题翻译：延迟链燃烧以增加物理不可靠功能的重复性
公开(公告)号：US20120081143A1
公开(公告)日：2012-04-05
申请号：US12898044
申请日：2010-10-05
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： H03K19/00
CPC分类号： G06F7/588 , H04L9/0866
摘要： A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
摘要翻译：电路和方法通过在芯片烧录期间通过两个延迟链增强信号延迟的变化来增加物理上不可检测的功能（PUF）的重复性。老化电路在老化过程中将两个延迟链的输入保持相反的随机值。延迟链中所有在输入端具有低电平值的PFET将以更高的导通电压进行烧录。由于在两个延迟链中受影响的PFET在老化期间被相反的转变驱动，所以两个延迟链中的延迟组件的交替组合受老化周期的影响。在正常操作下，两个延迟链看到相同的输入，所以只有一个链延迟增加，以实现两个延迟路径的统计上可靠的差异，从而增加了PUF电路的整体重复性。

7. 发明授权

US07924633B2 Implementing boosted wordline voltage in memories 有权
标题翻译：在存储器中实现提升的字线电压
公开(公告)号：US07924633B2
公开(公告)日：2011-04-12
申请号：US12389420
申请日：2009-02-20
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C8/08
摘要： A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.
摘要翻译：一种用于在存储器中实现升压的字线电压的方法和字线电压升压电路，以及设置有该电路所在的设计结构。字线升压电路接收预充电信号，使用耦合到自举电容器的开关晶体管，并响应于预充电信号产生升压电压电平。提升的电压电平被施加到字线驱动器的输出级的电压源，导致所选字线的字线电压电平升高。开关晶体管由预充电信号控制，并且提供升压电压电平的自举电容的节点由开关晶体管驱动为高电平。

8. 发明授权

US07768851B2 Apparatus for implementing SRAM cell write performance evaluation 失效
标题翻译：用于实现SRAM单元写入性能评估的装置
公开(公告)号：US07768851B2
公开(公告)日：2010-08-03
申请号：US12351920
申请日：2009-01-12
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

9. 发明申请

US20100046277A1 Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability 失效
标题翻译：实现具有增强的SRAM单元稳定性的Domino读取SRAM的本地评估
公开(公告)号：US20100046277A1
公开(公告)日：2010-02-25
申请号：US12195117
申请日：2008-08-20
申请人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
发明人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/413
摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.
摘要翻译：一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。能够对相关联的SRAM单元组进行读和写操作的SRAM本地评估电路包括真实和补码位线，单个写入数据传播输入，预充电信号和预充电写入信号。传递门装置连接在补码位线和写入数据传播输入之间。晶体管堆叠与真正位线和地之间的预充电装置串联连接。在读取操作期间，预充电写入信号禁止连接在补码位线和写入数据传播输入之间的通道器件。在写操作期间，预充电写入信号使得连接在补码位线和写入数据传播输入之间的通道器件能够激活晶体管堆叠。

10. 发明申请

US20100019824A1 Low Power Level Shifting Latch Circuits With Gated Feedback for High Speed Integrated Circuits 失效
标题翻译：具有门控反馈的低功率电平移位锁存电路用于高速集成电路
公开(公告)号：US20100019824A1
公开(公告)日：2010-01-28
申请号：US12178071
申请日：2008-07-23
申请人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
发明人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
IPC分类号： H03L5/00
CPC分类号： H03K3/356121
摘要： Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.
摘要翻译：具有用于高速集成电路的门控反馈的低功率电平移位器锁存电路，以及设有主题电路所在的设计结构。操作在第一电压源的域中的锁存器输入级接收响应于通过预定时钟信号使能的数据输入。耦合到锁存器输入级的锁存器存储元件包括在第二电压源的区域中操作的锁存器输出级提供具有与第二电压源相对应的电压电平的数据输出。闩锁存储元件包括电平移位装置，其提供从第一电源电平到第二电压供应电平的电平移位。锁存器存储元件包括反馈栅极器件，当数据被写入锁存器输入级时，反馈栅极器件接收预定义的时钟信号以对门锁反馈到锁存器输入级。

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