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1. 发明申请

US20070019454A1 Glitch protect valid cell and method for maintaining a desired state value 有权
标题翻译：毛刺保护有效的单元格和方法以保持所需的状态值
公开(公告)号：US20070019454A1
公开(公告)日：2007-01-25
申请号：US11184346
申请日：2005-07-19
申请人： Derick Behrends , Chad Adams , Ryan Kivimagi , Anthony Aipperspach , Robert Krentler
发明人： Derick Behrends , Chad Adams , Ryan Kivimagi , Anthony Aipperspach , Robert Krentler
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C7/24
摘要： A glitch protect valid cell and method for maintaining a desired logic state value in response to a glitch signal and a timing signal. The glitch protect valid cell may be integrated with a content addressable memory (CAM) array for indicating whether word data stored within the CAM is valid. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit each responsive to one another. The glitch protect circuit includes a propagation delay assembly and a restore assembly electrically coupled to one another. The propagation delay assembly includes a first pull down network and a NOR gate electrically coupled to one another. The restore assembly includes a second pull down network electrically coupled to the propagation delay assembly. The first pull down network is responsive to the glitch signal and the timing signal to selectively engage the NOR gate. In a glitch protect condition, the glitch protect valid cell restores the initial logic state value of the true valid bit despite at least one glitch signal invalidating the initial value. As such, the first pull down network resets the initial state value of the true valid bit according to the timing signal and the glitch signal supplied to the glitch protect circuit. The initial state value of a true valid bit is restored in the memory element with the second pull down network via the timing signal and a restore signal provided by an enabled pull up network within the NOR gate. Specifically, the second pull down network is responsive to the pull up network selectively enabled within the NOR gate and resets the complement valid bit in the memory element to consequently restore the initial state value of the true valid bit.
摘要翻译：毛刺保护有效单元和方法，用于响应于毛刺信号和定时信号来维持所需的逻辑状态值。毛刺保护有效单元可以与内容可寻址存储器（CAM）阵列集成，用于指示存储在CAM内的字数据是否有效。毛刺保护有效单元包括每个彼此响应的存储元件，状态机和毛刺保护电路。毛刺保护电路包括彼此电耦合的传播延迟组件和恢复组件。传播延迟组件包括彼此电耦合的第一下拉网络和或非门极。恢复组件包括电耦合到传播延迟组件的第二下拉网络。第一下拉网络响应于毛刺信号和定时信号以选择性地接合或非门。在毛刺保护条件下，尽管至少有一个毛刺信号使初始值无效，但毛刺保护有效单元仍恢复真有效位的初始逻辑状态值。这样，第一下拉网络根据提供给毛刺保护电路的定时信号和毛刺信号来重置真有效位的初始状态值。通过定时信号，通过第二下拉网络在存储器元件中恢复真有效位的初始状态值，以及由或非门内由使能的上拉网络提供的恢复信号。具体地，第二下拉网络响应于在或非门内选择性启用的上拉网络，并且重置存储器元件中的补码有效位，从而恢复真有效位的初始状态值。

2. 发明申请

US20070053231A1 Flood Mode Implementation for Continuous Bitline Local Evaluation Circuit 失效
标题翻译：连续位线局部评估电路的洪水模式实现
公开(公告)号：US20070053231A1
公开(公告)日：2007-03-08
申请号：US11552791
申请日：2006-10-25
申请人： Chad Adams , Derick Behrends , Ryan Kivimagi
发明人： Chad Adams , Derick Behrends , Ryan Kivimagi
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41
摘要： A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于采用连续位线局部评估电路的SRAM单元的泛洪模式实现。洪水模式测试用于通过强调SRAM单元来清除边缘SRAM单元。通过开始正常的写操作来引发洪泛模式。在新的数据值被强制进入SRAM单元之后，写入信号被切断。延迟块将字线信号保持在高电源，SRAM单元进入泛洪模式。在这个关键点，边缘细胞可以很容易地被检测，并且稍后映射到冗余细胞。

3. 发明申请

US20060092727A1 Flood mode implementation for continuous bitline local evaluation circuit 失效
公开(公告)号：US20060092727A1
公开(公告)日：2006-05-04
申请号：US10981153
申请日：2004-11-04
申请人： Chad Adams , Derick Behrends , Ryan Kivimagi
发明人： Chad Adams , Derick Behrends , Ryan Kivimagi
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C11/41
摘要： A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

4. 发明申请

US20050007813A1 Lower power and reduced device split local and continuous bitline for domino read SRAMs 有权
标题翻译：降低功耗和减少器件分割本地和连续位线用于多米诺式读取SRAM
公开(公告)号：US20050007813A1
公开(公告)日：2005-01-13
申请号：US10616847
申请日：2003-07-10
申请人： Chad Adams , Anthony Aipperspach , Todd Christensen , Peter Freiburger
发明人： Chad Adams , Anthony Aipperspach , Todd Christensen , Peter Freiburger
IPC分类号： G11C7/18 , G11C11/419 , G11C11/00
CPC分类号： G11C7/18 , G11C11/419
摘要： The present invention provides for reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line. The true node of the SRAM cell is evaluated through use of a floating voltage coupled to the true node of the SRAM cell. If the floating voltage stays substantially constant, the value read from the SRAM cell is a high. If the floating voltage is drained to ground, the value read from the SRAM cell is a low.
摘要翻译：本发明提供从SRAM单元读取标记。在写真线上生成一个低值。在连续的位线上生成高值。通过使用耦合到SRAM单元的真实节点的浮动电压来评估SRAM单元的真实节点。如果浮置电压保持大致恒定，则从SRAM单元读取的值为高。如果浮置电压耗尽地，则从SRAM单元读取的值为低电平。

5. 发明申请

US20070019461A1 Methods and apparatus for accessing memory 有权
标题翻译：访问内存的方法和设备
公开(公告)号：US20070019461A1
公开(公告)日：2007-01-25
申请号：US11186606
申请日：2005-07-21
申请人： Chad Adams , Anthony Aipperspach , Juergen Pille , Otto Wagner
发明人： Chad Adams , Anthony Aipperspach , Juergen Pille , Otto Wagner
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C7/06 , G11C7/1006 , G11C7/12
摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了访问存储器的第一种方法。第一种方法包括以下步骤：（1）将包含在具有排列成行和列的多个单元的存储器中的单元中存储位，其中每个单元包括一组晶体管，其适合于存储该位并影响被断言的信号在耦合到所述单元的位线上的读取操作期间，所述受影响的信号与存储在所述单元中的所述位的值相匹配; 并且（2）防止存储在单元中的位的值改变状态，同时晶体管组影响在耦合到单元的位线的读操作期间断言的信号。提供了许多其他方面。

6. 发明申请

US20070044049A1 Apparatus and methods for predicting and/or calibrating memory yields 失效
标题翻译：用于预测和/或校准记忆的装置和方法产生
公开(公告)号：US20070044049A1
公开(公告)日：2007-02-22
申请号：US11207068
申请日：2005-08-18
申请人： Chad Adams , Anthony Aipperspach , George Paulik
发明人： Chad Adams , Anthony Aipperspach , George Paulik
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An apparatus and methods for predicting and/or for calibrating memory yields due to process defects and/or device variations, including determining a model of a memory cell, identifying a subset of parameters associated with the model, determining and executing a refined model using the parameters, determining a predicted probability the simulated memory cell will be operational based on the simulated operation of the refined model, determining yield prediction information from the predicted probability, and determining the minimum number of repair elements to include in a memory array design to insure a desired yield percentage based on the yield prediction information.
摘要翻译：用于由于过程缺陷和/或设备变化而预测和/或校准存储器的装置和方法，包括确定存储器单元的模型，识别与模型相关联的参数的子集，使用参数，基于精炼模型的模拟操作确定模拟存储器单元将可操作的预测概率，根据预测概率确定收益率预测信息，以及确定修复元素的最小数量以包括在存储器阵列设计中以确保基于产量预测信息的期望产量百分比。

7. 发明申请

US20060250842A1 Methods and apparatus for accessing memory 有权
标题翻译：访问内存的方法和设备
公开(公告)号：US20060250842A1
公开(公告)日：2006-11-09
申请号：US11122805
申请日：2005-05-05
申请人： Chad Adams , Anthony Aipperspach
发明人： Chad Adams , Anthony Aipperspach
IPC分类号： G11C14/00
CPC分类号： G11C11/412
摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a first group of transistors adapted to store the bit and a second group of transistors adapted to affect a signal asserted during a read operation on a read bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the second group of transistors affects the signal asserted during the read operation on the read bit line coupled to the cell. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了访问存储器的第一种方法。第一种方法包括以下步骤：（1）将包含在具有布置成行和列的多个单元的存储器中的单元中存储位，其中每个单元包括适于存储该位的第一组晶体管和第二组晶体管适于影响在耦合到该单元的读取位线上的读取操作期间所确定的信号，使得受影响的信号与存储在该单元中的位的值相匹配; 和（2）防止存储在单元中的位的值改变状态，而第二组晶体管影响在读取操作期间对耦合到该单元的读位线断言的信号。提供了许多其他方面。

8. 发明申请

US20050251092A1 Needle assembly with tether 审中-公开
标题翻译：针组装与系绳
公开(公告)号：US20050251092A1
公开(公告)日：2005-11-10
申请号：US10842593
申请日：2004-05-10
申请人： Glade Howell , Chad Adams , Weston Harding , Chris Cindrich
发明人： Glade Howell , Chad Adams , Weston Harding , Chris Cindrich
IPC分类号： A61M25/06 , A61M5/00
CPC分类号： A61M25/0637 , A61M5/3275 , A61M25/0625
摘要： A needle assembly with needle shield that is connected to the needle hub by a tether. The tether prevents unwanted proximal movement of the needle with respect to the needle shield once the needle has been withdrawn into the needle shield. The tether is maintained in its compressed state by use of the invention for ease of assembly.
摘要翻译：带针罩的针头组件，通过系绳连接到针座。一旦针已经被抽出到针护罩中，系绳就可以防止针头相对于针罩的不需要的近端移动。为了便于组装，使用本发明将系绳保持在其压缩状态。

9. 发明申请

US20050080378A1 Method and apparatus for shielding the tip of a catheter introducer needle 有权
标题翻译：用于屏蔽导管导引针尖端的方法和装置
公开(公告)号：US20050080378A1
公开(公告)日：2005-04-14
申请号：US10477348
申请日：2003-06-20
申请人： Christopher Cindrich , Glade Howell , Weston Harding , Joseph Trodsham , Chad Adams
发明人： Christopher Cindrich , Glade Howell , Weston Harding , Joseph Trodsham , Chad Adams
IPC分类号： A61M5/32 , A61M5/158 , A61M25/00 , A61M25/06 , A61M5/178
CPC分类号： A61M5/3273 , A61M5/3275 , A61M25/0612 , A61M25/0625 , A61M2005/3247
摘要： A medical needle assembly includes a needle cannula having a body and a tip. The tip is disposed at a distal end of the cannula. An elongate member has a first end and a second end. The first end is fixedly attached to the body of the needle cannula at a connection point and the second end extends radially outward from the needle body. A shield is slidingly mounted to the needle for movement between a proximal position to a distal position. The shield includes a shield body having a central chamber, a distal end and a proximal end as well as a plate secured to the shield body and defining an aperture. As the shield is moved from the proximal position to the distal position, the place displaces the second end of the elongate member to a position near the needle cannula, permitting the elongate member to pass through the aperture. When the shield is in the distal position, the send end of the elongate member extends radially outward from the needle body, preventing passage of the elongate member through the aperture. The elongate member may be a leaf spring. A feature may be secured to the body of the cannula to restrict movement of the shield with respect to the needle.
摘要翻译：医疗针组件包括具有主体和尖端的针插管。尖端设置在套管的远端。细长构件具有第一端和第二端。第一端在连接点处固定地附接到针插管的主体，并且第二端从针体径向向外延伸。屏蔽件滑动地安装到针上以在近端位置到远端位置之间移动。护罩包括具有中心室，远端和近端的屏蔽体以及固定到屏蔽体并限定孔的板。当护罩从近侧位置移动到远端位置时，该位置将细长构件的第二端移动到靠近针管的位置，允许细长构件穿过孔。当护罩处于远侧位置时，细长构件的送出端从针体径向向外延伸，从而防止细长构件穿过孔的通道。细长构件可以是板簧。特征可以固定到套管的主体以限制护罩相对于针的移动。

10. 发明授权

US06717758B2 Disk partitioning to create a usable, lower capacity disk cartridge 有权
标题翻译：磁盘分区，创建一个可用的，低容量的磁盘盒
公开(公告)号：US06717758B2
公开(公告)日：2004-04-06
申请号：US09854719
申请日：2001-05-15
申请人： Chad Adams , Eric Ryon Peters , Robert L. Short , Mark Reimann , Daniel D. Rochat
发明人： Chad Adams , Eric Ryon Peters , Robert L. Short , Mark Reimann , Daniel D. Rochat
IPC分类号： G11B2736
CPC分类号： G11B20/1217 , G11B2020/1232 , G11B2020/1285 , G11B2220/2537
摘要： A disk is manufactured having a reduced capacity based on a quantity of addressable and non-addressable portions. The method of formatting the disk comprises identifying a first quantity of the storage portions; and labeling the first quantity of storage portions as non-addressable storage portions such that the non-addressable storage portions cannot be accessed by a user or a disk drive. The first quantity of storage portions may include addressable portions designated as non-addressable portions.
摘要翻译：基于可寻址和不可寻址部分的数量，制造具有减小的容量的盘。格式化盘的方法包括：识别第一数量的存储部分; 以及将第一数量的存储部分标记为不可寻址存储部分，使得不可寻址存储部分不能被用户或磁盘驱动器访问。第一数量的存储部分可以包括被指定为不可寻址部分的寻址部分。

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