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1. 发明申请

US20130215693A1 TRACKING CAPACITIVE LOADS 有权
标题翻译：跟踪电容负载
公开(公告)号：US20130215693A1
公开(公告)日：2013-08-22
申请号：US13399877
申请日：2012-02-17
申请人： Derek C. TAO , Young Seog KIM , Kuoyuan (Peter) HSU , Bing WANG , Annie-Li-Keow LUM
发明人： Derek C. TAO , Young Seog KIM , Kuoyuan (Peter) HSU , Bing WANG , Annie-Li-Keow LUM
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C7/222 , G11C11/41 , G11C29/50012 , G11C2029/5002
摘要： A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
摘要翻译：确定时间延迟以覆盖具有跟踪电路的存储器宏中的存储器单元的定时。基于时间延迟，确定与时间延迟相对应的电容。使用具有确定的电容的电容器。电容器耦合到跟踪电路的跟踪单元的第一数据线。第一数据线的第一转变导致存储器单元的第二数据线的第一转变。

2. 发明申请

US20130088926A1 TRACKING MECHANISMS 有权
标题翻译：跟踪机制
公开(公告)号：US20130088926A1
公开(公告)日：2013-04-11
申请号：US13253749
申请日：2011-10-05
申请人： Derek C. TAO , Annie-Li-Keow LUM , Yukit TANG , Kuoyuan (Peter) HSU
发明人： Derek C. TAO , Annie-Li-Keow LUM , Yukit TANG , Kuoyuan (Peter) HSU
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C11/419
摘要： A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.
摘要翻译：跟踪信号的跟踪边缘被激活。基于跟踪信号的跟踪边缘，缓冲器被关闭并且锁存电路被接通。缓冲器的缓冲器输出耦合到节点处的锁存电路的锁存器输出。缓冲区接收一个内存宏的数据行。

3. 发明申请

US20140269026A1 TRACKING CIRCUIT 有权
标题翻译：跟踪电路
公开(公告)号：US20140269026A1
公开(公告)日：2014-09-18
申请号：US13840668
申请日：2013-03-15
申请人： Derek C. TAO , Annie-Li-Keow LUM , Kuoyuan (Peter) HSU
发明人： Derek C. TAO , Annie-Li-Keow LUM , Kuoyuan (Peter) HSU
IPC分类号： G11C7/22
CPC分类号： G11C7/227 , G11C11/419
摘要： A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal.
摘要翻译：电路位于存储器宏中，并且包括写入路径，读取路径，选择电路和时钟发生器电路。写入路径包括在存储器宏的写入操作中基于时钟信号的第一边缘生成的第一信号。读取路径包括在存储器宏的读取操作中基于时钟信号的第一边缘生成的第二信号。选择电路被配置为在存储器宏的写入操作中选择第一信号作为第三信号，并且在存储器宏的读取操作中选择第二信号作为第三信号。时钟发生器电路被配置为在写入操作或基于第三信号的读取操作中产生时钟信号的第二边沿。

4. 发明申请

US20120182819A1 RECYCLING CHARGES 有权
标题翻译：回收费
公开(公告)号：US20120182819A1
公开(公告)日：2012-07-19
申请号：US13429082
申请日：2012-03-23
申请人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
发明人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
IPC分类号： G11C5/14 , G05F3/02
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译：电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管，耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管，其具有耦合到第二节点的源极，耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。当第一PMOS晶体管，控制晶体管和第一NMOS晶体管导通时，第一节点电压降低，而第二电压升高。

5. 发明申请

US20120019312A1 RECYCLING CHARGES 有权
公开(公告)号：US20120019312A1
公开(公告)日：2012-01-26
申请号：US12843366
申请日：2010-07-26
申请人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
发明人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
IPC分类号： G05F3/02
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.

6. 发明申请

US20120014201A1 DUAL RAIL MEMORY 有权
标题翻译：双轨记忆
公开(公告)号：US20120014201A1
公开(公告)日：2012-01-19
申请号：US12835197
申请日：2010-07-13
申请人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
发明人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译：一种存储器，包括：布置成多行和多列的多个存储单元。所述多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点，电耦合在一起并被配置为接收第一电压或该列中的多个存储单元的第二电压和多个内部接地节点。内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。

7. 发明申请

US20130010560A1 GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS 有权
标题翻译：生成和放大差分信号
公开(公告)号：US20130010560A1
公开(公告)日：2013-01-10
申请号：US13535075
申请日：2012-06-27
申请人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
发明人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
IPC分类号： H03F3/45 , G11C7/06
CPC分类号： G11C7/067 , G11C7/065
摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.
摘要翻译：电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。第一电流镜电路具有参考端和镜像端。第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。第二个当前次级电路具有参考端和镜像端。第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

8. 发明申请

US20100246311A1 CLOCK GENERATORS, MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING AN INTERNAL CLOCK SIGNAL 有权
标题翻译：用于提供内部时钟信号的时钟发生器，存储器电路，系统和方法
公开(公告)号：US20100246311A1
公开(公告)日：2010-09-30
申请号：US12723077
申请日：2010-03-12
申请人： Derek C. TAO , Chung-Ji LU , Annie-Li-Keow LUM
发明人： Derek C. TAO , Chung-Ji LU , Annie-Li-Keow LUM
IPC分类号： G11C8/18 , G06F1/04
CPC分类号： G06F1/10 , G11C7/22 , G11C7/222 , G11C11/413
摘要： A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period.
摘要翻译：时钟发生器包括第一输入端和第二输入端。第一输入端能够接收包括定义第一脉冲宽度的第一状态转变和第二状态转换的第一时钟信号。第二输入端能够接收具有第三状态转换的第二时钟信号。时间段从第一状态转换到第三状态转换。时钟发生器可以比较第一个脉冲宽度和时间周期。时钟发生器可以输出具有从第四状态转变到第五状态转变的第二脉冲宽度的第三时钟信号。根据第一脉冲宽度与时间段的比较，第三时钟信号的第五状态转换能够被第一时钟信号的第二状态转换或第二时钟信号的第三状态转换触发。

9. 发明申请

US20120051160A1 MULTIPLE BITCELLS TRACKING SCHEME FOR SEMICONDUCTOR MEMORIES 有权
标题翻译：用于半导体存储器的多个位元跟踪方案
公开(公告)号：US20120051160A1
公开(公告)日：2012-03-01
申请号：US12868909
申请日：2010-08-26
申请人： Derek C. TAO , Annie-Li-Keow LUM , Chung-Ji LU
发明人： Derek C. TAO , Annie-Li-Keow LUM , Chung-Ji LU
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/50012 , G11C11/41
摘要： A semiconductor memory segment includes a first memory bank having a first tracking cell disposed in a first tracking column. A second memory bank includes a second tracking cell disposed in a second tracking column. A first tracking circuit is coupled to the first and second tracking cells and is configured to output a first signal to memory control circuitry when the first and second tracking cells are accessed. The memory control circuitry is configured to set a clock based on the first signal.
摘要翻译：半导体存储器段包括具有设置在第一跟踪列中的第一跟踪单元的第一存储体。第二存储器组包括设置在第二跟踪列中的第二跟踪单元。第一跟踪电路耦合到第一和第二跟踪单元，并且被配置为当第一和第二跟踪单元被访问时，将第一信号输出到存储器控制电路。存储器控制电路被配置为基于第一信号设置时钟。

10. 发明申请

US20120020169A1 TWO-PORT SRAM WRITE TRACKING SCHEME 有权
标题翻译：双端口SRAM写入跟踪方案
公开(公告)号：US20120020169A1
公开(公告)日：2012-01-26
申请号：US12839624
申请日：2010-07-20
申请人： Bing WANG , Kuoyuan (Peter) HSU , Derek C. TAO
发明人： Bing WANG , Kuoyuan (Peter) HSU , Derek C. TAO
IPC分类号： G11C7/10
CPC分类号： G11C11/419 , G11C11/413
摘要： A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.
摘要翻译：静态随机存取存储器（SRAM）包括共享读位线（RBL）和写位线（WBL）的至少两个存储器单元。每个存储单元耦合到相应的读字线（RWL）和相应的写字线（WWL）。写跟踪控制电路耦合到存储器单元，以确定存储器单元的写入时间。写跟踪控制电路能够接收输入电压并提供输出电压。在写跟踪操作期间，各存储单元的相应RWL和相应的WWL被断言。

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