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1. 发明授权

US07545034B2 Thermal energy removal structure and method 有权
标题翻译：热能消除结构与方法
公开(公告)号：US07545034B2
公开(公告)日：2009-06-09
申请号：US11767850
申请日：2007-06-25
申请人： Deok-kee Kim , Wai-Kin Li , Haining Sam Yang
发明人： Deok-kee Kim , Wai-Kin Li , Haining Sam Yang
IPC分类号： H01L23/34
CPC分类号： H05K7/205 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： An electrical structure including a first substrate comprising a plurality of electrical components, a first thermally conductive film layer formed over and in contact with a first electrical component of the plurality of electrical components, a first thermally conductive structure in mechanical contact with a first portion of the first thermally conductive film layer, and a first thermal energy extraction structure formed over the first thermally conductive structure. The first thermal energy extraction structure is in thermal contact with the first thermally conductive structure. The first thermal energy extraction structure is configured to extract a first portion of thermal energy from the first electrical component through the first thermally conductive film layer and the first thermally conductive structure.
摘要翻译：一种电气结构，包括包括多个电气部件的第一基板，形成在所述多个电气部件中的第一电气部件上并与之接触的第一导热膜层，与所述多个电气部件的第一部分机械接触的第一导热结构第一导热膜层和形成在第一导热结构上的第一热能提取结构。第一热能提取结构与第一导热结构热接触。第一热能提取结构被配置为从第一电气部件通过第一导热膜层和第一导热结构提取热能的第一部分。

2. 发明申请

US20090090994A1 ELECTROMIGRATION FUSE AND METHOD OF FABRICATING SAME 有权
标题翻译：电磁保险丝及其制造方法
公开(公告)号：US20090090994A1
公开(公告)日：2009-04-09
申请号：US11869227
申请日：2007-10-09
申请人： Deok-kee Kim , Haining Sam Yang
发明人： Deok-kee Kim , Haining Sam Yang
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer comprising a cathode region, an anode region, a link region between the cathode and anode regions and a transition region between the cathode region and the link region, the transition region proximate to the sidewall of the cathode stack, the cathode region on a top surface of the cathode stack, the link region on a top surface of the dielectric layer, both a first thickness of the cathode region and a second thickness of the link region greater than a third thickness of the transition region; and a metal silicide layer on a top surface of the polysilicon layer.
摘要翻译：保险丝和形成保险丝的方法。保险丝包括：半导体衬底上的电介质层; 电介质层上的阴极堆叠，阴极堆叠的侧壁从阴极堆叠的顶表面延伸到电介质层的顶表面; 连续多晶硅层，包括阴极区域，阳极区域，阴极和阳极区域之间的连接区域以及阴极区域和连接区域之间的过渡区域，靠近阴极堆叠侧壁的过渡区域，阴极区域在阴极堆叠的顶表面上，电介质层的顶表面上的连接区域，阴极区域的第一厚度和连接区域的第二厚度大于过渡区域的第三厚度; 以及在所述多晶硅层的顶表面上的金属硅化物层。

3. 发明申请

US20080316709A1 Thermally Conductive Electrical Structure and Method 有权
标题翻译：导电电气结构与方法
公开(公告)号：US20080316709A1
公开(公告)日：2008-12-25
申请号：US11767850
申请日：2007-06-25
申请人： Deok-kee Kim , Wai-Kin Li , Haining Sam Yang
发明人： Deok-kee Kim , Wai-Kin Li , Haining Sam Yang
IPC分类号： H05K7/20
CPC分类号： H05K7/205 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： An electrical structure and method of forming. The electrical structure includes a first substrate comprising a plurality of electrical components, a first thermally conductive film layer formed over and in contact with a first electrical component of the plurality of electrical components, a first thermally conductive structure in mechanical contact with a first portion of the first thermally conductive film layer, and a first thermal energy extraction structure formed over the first thermally conductive structure. The first thermal energy extraction structure is in thermal contact with the first thermally conductive structure. The first thermal energy extraction structure is configured to extract a first portion of thermal energy from the first electrical component through the first thermally conductive film layer and the first thermally conductive structure.
摘要翻译：一种电气结构和成型方法。电结构包括包括多个电气部件的第一基板，形成在多个电气部件中的第一电气部件上并与其接触的第一导热膜层，与第一部分的第一部分机械接触的第一导热结构第一导热膜层和形成在第一导热结构上的第一热能提取结构。第一热能提取结构与第一导热结构热接触。第一热能提取结构被配置为从第一电气部件通过第一导热膜层和第一导热结构提取热能的第一部分。

4. 发明授权

US07709928B2 Electromigration fuse and method of fabricating same 有权
标题翻译：电流保险丝及其制造方法
公开(公告)号：US07709928B2
公开(公告)日：2010-05-04
申请号：US11869227
申请日：2007-10-09
申请人： Deok-kee Kim , Haining Sam Yang
发明人： Deok-kee Kim , Haining Sam Yang
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer comprising a cathode region, an anode region, a link region between the cathode and anode regions and a transition region between the cathode region and the link region, the transition region proximate to the sidewall of the cathode stack, the cathode region on a top surface of the cathode stack, the link region on a top surface of the dielectric layer, both a first thickness of the cathode region and a second thickness of the link region greater than a third thickness of the transition region; and a metal silicide layer on a top surface of the polysilicon layer.
摘要翻译：保险丝和形成保险丝的方法。保险丝包括：半导体衬底上的电介质层; 电介质层上的阴极堆叠，阴极堆叠的侧壁从阴极堆叠的顶表面延伸到电介质层的顶表面; 连续多晶硅层，包括阴极区域，阳极区域，阴极和阳极区域之间的连接区域以及阴极区域和连接区域之间的过渡区域，靠近阴极堆叠侧壁的过渡区域，阴极区域在阴极堆叠的顶表面上，电介质层的顶表面上的连接区域，阴极区域的第一厚度和连接区域的第二厚度大于过渡区域的第三厚度; 以及在所述多晶硅层的顶表面上的金属硅化物层。

5. 发明申请

US20090085151A1 SEMICONDUCTOR FUSE STRUCTURE AND METHOD 审中-公开
标题翻译：半导体熔丝结构和方法
公开(公告)号：US20090085151A1
公开(公告)日：2009-04-02
申请号：US11863814
申请日：2007-09-28
申请人： Deok-kee Kim , Wai-kin Li , Haining Sam Yang
发明人： Deok-kee Kim , Wai-kin Li , Haining Sam Yang
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrical structure and method of forming. The electrical structure includes a semiconductor substrate, an insulator layer formed over and in contact with the semiconductor substrate, and a semiconductor fuse structure formed over the insulator layer. The fuse structure includes a silicon layer and a continuous metallic silicide layer. The continuous metallic silicide layer includes a first section formed over and in contact with a first horizontal section of a top surface of the silicon layer, a second section formed over and in contact with a second horizontal section of the top surface of the silicon layer, and a third section formed within an opening within the top surface of the silicon layer.
摘要翻译：一种电气结构和成型方法。电结构包括半导体衬底，形成在半导体衬底上并与半导体衬底接触的绝缘体层，以及形成在绝缘体层上的半导体熔丝结构。熔丝结构包括硅层和连续的金属硅化物层。连续金属硅化物层包括形成在硅层的顶表面的第一水平部分上并与其接触的第一部分，形成在硅层的顶表面的第二水平部分上并与其接触的第二部分，以及形成在所述硅层的顶表面内的开口内的第三部分。

6. 发明授权

US08559207B2 Variable resistance memory device with trigger circuit for set/reset write operations 有权
标题翻译：可变电阻存储器件，具有用于置位/复位写入操作的触发电路
公开(公告)号：US08559207B2
公开(公告)日：2013-10-15
申请号：US13009077
申请日：2011-01-19
申请人： Deok-kee Kim , Ho Jung Kim
发明人： Deok-kee Kim , Ho Jung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C2013/0066 , G11C2213/72
摘要： A variable resistance memory device comprises a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage from the input terminal upon determining that the variable resistance memory cell is programmed to a target state by detecting voltage fluctuation of the one side of variable resistance memory cell.
摘要翻译：可变电阻存储器件包括可变电阻存储单元，选择性地将写入电压传递到可变电阻存储单元的输入端的开关，以及触发电路，其控制开关从输入端截取写入电压，通过检测可变电阻存储单元的一侧的电压波动来确定可变电阻存储单元被编程为目标状态。

7. 发明授权

US08526258B2 Variable resistance memory device and related method of operation 有权
标题翻译：可变电阻存储器件及相关操作方法
公开(公告)号：US08526258B2
公开(公告)日：2013-09-03
申请号：US13026456
申请日：2011-02-14
申请人： Deok-kee Kim , Ho Jung Kim
发明人： Deok-kee Kim , Ho Jung Kim
IPC分类号： G11C7/02
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0071
摘要： A variable resistance memory device comprises a memory cell comprising a variable resistance device and a select transistor connected in series to the variable resistance device. The variable resistance memory device further comprises a write driver for supplying a write voltage to opposite sides of the memory cell, and a feedback circuit for detecting a resistance change of the variable resistance device and controlling a gate voltage of the select transistor according to the detected resistance change.
摘要翻译：可变电阻存储器件包括存储单元，该存储单元包括与可变电阻器件串联连接的可变电阻器件和选择晶体管。可变电阻存储器件还包括写入驱动器，用于向存储单元的相对侧提供写入电压;以及反馈电路，用于检测可变电阻器件的电阻变化，并根据检测到的来控制选择晶体管的栅极电压阻力变化。

8. 发明授权

US08247788B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08247788B2
公开(公告)日：2012-08-21
申请号：US12659175
申请日：2010-02-26
申请人： Kwang-soo Seol , Yoon-dong Park , Deok-kee Kim , Sang-jun Choi
发明人： Kwang-soo Seol , Yoon-dong Park , Deok-kee Kim , Sang-jun Choi
IPC分类号： H01L45/00
CPC分类号： H01L27/2445 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147
摘要： The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor.
摘要翻译：非易失性存储器件包括至少一对第一电极线，设置在至少一对第一电极线之间的至少一个器件结构和设置在该至少一个器件结构与至少一对第一电极线之间的电介质层电极线。所述至少一个器件结构包括第二电极线，所述第二电极线包括第一导电类型半导体，与所述第二电极线相邻的电阻改变材料层，与所述电阻变化材料层相邻的通道，并且包括不同于所述第一导电类型的第一导电型半导体导电型半导体和与沟道相邻的第三电极线，并且包括第一导电型半导体。

9. 发明授权

US08159040B2 Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor 有权
标题翻译：金属栅极集成结构和方法，包括金属保险丝，反熔丝和/或电阻
公开(公告)号：US08159040B2
公开(公告)日：2012-04-17
申请号：US12119526
申请日：2008-05-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
IPC分类号： H01L29/00
CPC分类号： H01L27/0629 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
摘要翻译：半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料栅电极。

10. 发明授权

US08058701B2 Antifuse structures, antifuse array structures, methods of manufacturing the same 有权
标题翻译：防污结构，反熔丝阵列结构，制造方法
公开(公告)号：US08058701B2
公开(公告)日：2011-11-15
申请号：US12216094
申请日：2008-06-30
申请人： Deok-kee Kim , Yoon-dong Park , Seung-hoon Lee , I-hun Song , Won-joo Kim , Young-gu Jin , Hyuk-soon Choi , Suk-pil Kim
发明人： Deok-kee Kim , Yoon-dong Park , Seung-hoon Lee , I-hun Song , Won-joo Kim , Young-gu Jin , Hyuk-soon Choi , Suk-pil Kim
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , G11C17/16 , H01L27/1021 , H01L2924/0002 , H01L2924/00
摘要： Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.
摘要翻译：提供了防泡结构，反熔丝阵列，制造方法和操作方法。反熔丝结构包括在半导体衬底内形成为第一扩散区的位线，形成在位线上的绝缘层，以及形成在绝缘层上的字线。反熔丝阵列包括排列成阵列的多个反熔丝结构。

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