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1. 发明专利

JP2012019594A Piezo actuator drive device 审中-公开
标题翻译： PIEZO执行器驱动装置
公开(公告)号：JP2012019594A
公开(公告)日：2012-01-26
申请号：JP2010154917
申请日：2010-07-07
申请人： Denso Corp , Nippon Soken Inc , 株式会社デンソー , 株式会社日本自動車部品総合研究所
发明人： FUKAGAWA YASUHIRO , NAOI TAKASHI , AOKI TAKAAKI
IPC分类号： H02N2/00
CPC分类号： F02D41/2096 , F02D2041/2086 , F02M51/0603 , F02M2200/21 , H02N2/067
摘要： PROBLEM TO BE SOLVED: To reduce noise generated from a piezo actuator drive device.SOLUTION: In a piezo actuator drive device 1, during execution of charge/discharge control by a charge/discharge control unit 17, when a current detection unit 16 is detecting a piezo current, a noise propagation prevention switch control unit 19 turns on a noise propagation prevention switch 18 and when the current detection unit 16 is not detecting a piezo current, the noise propagation prevention switch control unit 19 turns off the noise propagation prevention switch 18. This makes it possible to, while a flywheel current is zero, block a current path of a resonance circuit, which is constructed by a diode Da/diode Db, a coil for charge/discharge 11, and a piezo actuator 50, with a noise propagation prevention switch 18, which enables suppression of noise generation ascribable to the resonance circuit.
摘要翻译：要解决的问题：减少压电致动器驱动装置产生的噪音。解决方案：在压电致动器驱动装置1中，在由充放电控制单元17执行充放电控制期间，当电流检测单元16检测压电电流时，噪声传播防止开关控制单元19转动在噪声传播防止开关18上，并且当电流检测单元16没有检测到压电电流时，噪声传播防止开关控制单元19关闭噪声传播防止开关18.这使得可以在飞轮电流为零阻挡由二极管Da /二极管Db，充电/放电线圈11和压电致动器50构成的谐振电路的电流路径，具有噪声传播防止开关18，能够抑制噪声产生到谐振电路。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2009296216A Switching drive circuit, and switching circuit 审中-公开
标题翻译：切换驱动电路和切换电路
公开(公告)号：JP2009296216A
公开(公告)日：2009-12-17
申请号：JP2008146779
申请日：2008-06-04
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： HATTORI YOSHIKUNI , KUWABARA MAKOTO , NAKANO TAKASHI , TAKAHASHI SHIGEKI , MIZUNO SHOJI , AOKI TAKAAKI , SUMITOMO MASAKIYO
IPC分类号： H03K17/16 , H02M1/08 , H02M3/155 , H03K17/695
摘要： PROBLEM TO BE SOLVED: To provide a technique that reduces harmonic noise, as well as, suppresses increase in switching loss. SOLUTION: This switching drive circuit 11 has temporal change-over of a conduction state change-over to a non-conduction state and vice versa, between a drain electrode and a source electrode of a transistor Tr10, by changing a gate voltage Vg of the transistor Tr10. The switching drive circuit 11 is provided with a variable capacitance element 14, connected between the drain electrode D and an gate electrode G of the transistor Tr10. The capacitance of the variable capacitance element 14 is such that it is lowered, when the potential difference between the drain electrode D and the gate electrode G of the transistor Tr10 is increased. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供减少谐波噪声的技术，以及抑制开关损耗的增加。解决方案：该开关驱动电路11通过改变栅极电压，在晶体管Tr10的漏极和源极之间具有导通状态转换到非导通状态的时间转换，反之亦然晶体管Tr10的Vg。开关驱动电路11设置有连接在漏电极D和晶体管Tr10的栅电极G之间的可变电容元件14。当晶体管Tr10的漏电极D和栅电极G之间的电位差增加时，可变电容元件14的电容降低。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2008277324A Semiconductor device having vertical mosfet 审中-公开
标题翻译：具有垂直MOSFET的半导体器件
公开(公告)号：JP2008277324A
公开(公告)日：2008-11-13
申请号：JP2007115581
申请日：2007-04-25
申请人： Denso Corp , 株式会社デンソー
发明人： SHIGA TOMOHIDE , AOKI TAKAAKI
IPC分类号： H01L27/04 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing feedback loss mainly caused by Vf of a body diode.
SOLUTION: The semiconductor device has a structure in which an AccuFET or a J-FET is also formed by adding DMOS in one chip. This configuration disables a feedback current to flow to DMOS side but enables it to flow to the AccuFET side or J-FET side. It also provides an effect of reducing a loss mainly caused by Vf of the body diode.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够减少主要由体二极管的Vf引起的反馈损失的半导体器件。解决方案：半导体器件具有其中通过在一个芯片中添加DMOS也形成AccuFET或J-FET的结构。该配置禁止反馈电流流向DMOS端，但可使其流向AccuFET侧或J-FET侧。它还提供减少主要由体二极管的Vf引起的损耗的效果。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008270258A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2008270258A
公开(公告)日：2008-11-06
申请号：JP2007107071
申请日：2007-04-16
申请人： Denso Corp , 株式会社デンソー
发明人： SHIGA TOMOHIDE , AOKI TAKAAKI
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which the threshold voltage Vt of the gate electrode can be adjusted to a target value.
SOLUTION: A trench 14 is formed on the surface side of semiconductor substrates 10-13, an ONO film 18 consisting of a silicon oxide film 15, a silicon nitride film 16 and a silicon oxide film 17 is formed in the trench 14 and a gate electrode 20 is formed on the ONO film 18, and then a source electrode 23 and a backside metal electrode 24 are formed, respectively, on the surface and the backside of the semiconductor substrates 10-13. Subsequently, carriers are injected into the silicon nitride film 16 by applying an electric field to the gate electrode 20 and an electric field to the silicon nitride film 16 in the ONO film 18, thus shifting the threshold voltage Vt of the gate electrode 20 to the target value (fig. 3(c)).
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件的制造方法，其中可以将栅电极的阈值电压Vt调节到目标值。解决方案：在半导体衬底10-13的表面侧上形成沟槽14，在沟槽14中形成由氧化硅膜15，氮化硅膜16和氧化硅膜17组成的ONO膜18 并且在ONO膜18上形成栅电极20，然后在半导体衬底10-13的表面和背面分别形成源电极23和背面金属电极24。随后，通过向栅电极20施加电场，并向ONO膜18中的氮化硅膜16施加电场，将载流子注入到氮化硅膜16中，从而将栅电极20的阈值电压Vt移位到目标值（图3（c））。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2003318394A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003318394A
公开(公告)日：2003-11-07
申请号：JP2002117590
申请日：2002-04-19
申请人： Denso Corp , 株式会社デンソー
发明人： OKURA YASUTSUGU , AOKI TAKAAKI
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve a gate-source withstand voltage in a gate lead wiring region, in a trench gate type semiconductor device of a mesh structure.
SOLUTION: In the trench gate type semiconductor device of the mesh structure, a dummy cell connected to a cell formed in a cell region is contained in the gate lead wiring region. Gate lead wiring 18 is connected to a trench gate 16 in the dummy cell. The dummy cell has the trench gate 16 of the same mesh structure as the cell, meanwhile the dummy cell is not electrically connected to a source electrode 10.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了提高网格结构的沟槽栅型半导体器件中栅极引线布线区域中的栅极 - 源极耐受电压。解决方案：在网格结构的沟槽栅型半导体器件中，连接到形成在单元区域中的单元的虚拟单元包含在栅极引线布线区域中。栅极引线布线18连接到虚拟单元中的沟槽栅极16。虚拟电池具有与电池相同的网格结构的沟槽栅极16，同时虚设电池不与源电极10电连接。版权所有（C）2004，JPO

6. 发明专利

JP2008054280A Driving circuit for transistor 有权
标题翻译：驱动电路用于晶体管
公开(公告)号：JP2008054280A
公开(公告)日：2008-03-06
申请号：JP2007073381
申请日：2007-03-20
申请人： Denso Corp , Toyota Central R&D Labs Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： HATSUTORI YOSHIKUNI , KUWABARA MAKOTO , OKADA KYOKO , MIZUNO SHOJI , AOKI TAKAAKI , TAKAHASHI SHIGEKI , AKAGI NOZOMI , NAKANO TAKASHI
IPC分类号： H03K17/08 , H01L21/822 , H01L27/04 , H03K17/06 , H03K17/695
摘要： PROBLEM TO BE SOLVED: To overcome a trade-off relationship between a surge voltage and a turn-off loss that exists within a transition time period for turning off a transistor, in a circuit for driving the transistor. SOLUTION: A driving circuit 10 comprises a variable resistor R12 that is electrically connected to a gate electrode G of a transistor 20. A width of a current path of the variable resistor R12 is controlled by a depletion layer which is expandable in accordance with a drain-source voltage Vds of the transistor 20. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：在用于驱动晶体管的电路中，克服在用于关断晶体管的转变时间段内存在的浪涌电压和关断损耗之间的权衡关系。解决方案：驱动电路10包括电连接到晶体管20的栅电极G的可变电阻器R12。可变电阻器R12的电流通路的宽度由耗尽层控制，该耗尽层根据具有晶体管20的漏 - 源电压Vds。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2008035068A Driving circuit for transistor 有权
标题翻译：驱动电路用于晶体管
公开(公告)号：JP2008035068A
公开(公告)日：2008-02-14
申请号：JP2006204769
申请日：2006-07-27
申请人： Denso Corp , Toyota Central Res & Dev Lab Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： KUWABARA MAKOTO , HATSUTORI YOSHIKUNI , OKADA KYOKO , MIZUNO SHOJI , AOKI TAKAAKI , TAKAHASHI SHIGEKI , AKAGI NOZOMI , NAKANO TAKASHI
IPC分类号： H03K17/687 , H02M1/08
摘要： PROBLEM TO BE SOLVED: To break down a trade-off relation between a serge voltage and a turn-off loss existing in a transitional stage in which a transistor is turned off in a circuit for driving the transistor.
SOLUTION: A driving circuit 10 is provided with an adjustment circuit 20 for adjusting the resistance value of the gate resistance of a transistor 30. An adjustment circuit 20 adjusts the resistance value of the gate resistance of the transistor gate 30 based on the current value of the negative gate currents Ig(-) of the transistor 30. Thus, the driving circuit 10 rapidly varies drain currents at the beginning of the transitional stage when the transistor 30 is turned off, and slowly varies the drain currents in the end of the transitional stage when the transistor 30 is turned off.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：分解在用于驱动晶体管的电路中晶体管截止的过渡阶段中存在的脉冲电压和关断损耗之间的权衡关系。解决方案：驱动电路10设置有用于调整晶体管30的栅极电阻的电阻值的调整电路20.调节电路20基于该晶体管30的栅极电阻的电阻值调整晶体管栅极30的栅极电阻晶体管30的负栅极电流Ig（ - ）的电流值。因此，当晶体管30截止时，驱动电路10在过渡阶段开始时迅速地改变漏极电流，并且最终缓慢地改变漏极电流当晶体管30截止时，该过渡阶段。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2008021930A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008021930A
公开(公告)日：2008-01-31
申请号：JP2006194527
申请日：2006-07-14
申请人： Denso Corp , 株式会社デンソー
发明人： AOKI TAKAAKI , FUJII TETSUO
IPC分类号： H01L29/78 , H01L29/423 , H01L29/49 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device constituted by juxtaposing an MOS and an SBD on a semiconductor substrate, superior in recovery characteristic of a diode, reducible in forward direction loss, free of decreases in breakdown voltage and surge tolerance, superior in switching characteristic, compact in structure, and inexpensive.
SOLUTION: The semiconductor device 100 has embedded trenches T1 and T2 formed linearly without crossing each other, and a predetermined region at a surface layer divided into a plurality of partition regions R1 and R2. In the first partition region R1, a layer 33 of a second conductivity type to become a channel of the MOS is formed, polycrystalline silicon in the first embedded trench T1 is connected to a gate wiring, and polycrystalline silicon in the second embedded trench T2 is connected to a source wiring or the gate wiring. In the second partition region R2, a layer 30a of a first conductivity type is exposed on a surface and connected to the source wiring, and a Schottky barrier is formed.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种通过在半导体衬底上并置MOS和SBD构成的半导体器件，二极管的恢复特性优异，可以在正向损耗下减小，没有击穿电压和浪涌容限的降低，开关特性优越，结构紧凑，价格便宜。解决方案：半导体器件100具有线性形成的嵌入沟槽T1和T2，而不是彼此交叉形成，并且表面层上划分为多个分割区域R1和R2的预定区域。在第一分区区域R1中，形成第二导电类型的成为MOS沟道的层33，第一嵌入沟槽T1中的多晶硅连接到栅极布线，第二嵌入沟槽T2中的多晶硅为连接到源极接线或栅极接线。在第二分割区域R2中，第一导电类型的层30a暴露在表面上并连接到源极布线，并且形成肖特基势垒。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007295543A Switching circuit 审中-公开
标题翻译：切换电路
公开(公告)号：JP2007295543A
公开(公告)日：2007-11-08
申请号：JP2007073382
申请日：2007-03-20
申请人： Denso Corp , Toyota Central Res & Dev Lab Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： HATSUTORI YOSHIKUNI , KUWABARA MAKOTO , OKADA KYOKO , MIZUNO SHOJI , AOKI TAKAAKI
IPC分类号： H03K17/16 , H02M1/00 , H02M1/08 , H03K17/06 , H03K17/56 , H03K17/687
摘要： PROBLEM TO BE SOLVED: To provide a switching circuit capable of simultaneously suppressing both a switching loss and a surge voltage. SOLUTION: The present invention relates to a switching circuit for temporally switching main electrodes of a transistor between a conducted state and a non-conducted state by switching a gate voltage of the transistor, wherein a drain or a collector of the transistor and its gate or the drain or the collector of the transistor and its source or its emitter are connected by a series circuit of a Zener diode and a capacitor. While a drain voltage is low, a state is judged where capacitance of the capacitor is not contributed by the Zener diode, a drain current and the drain voltage vary at high speed, thereby reducing the switching loss. When the drain voltage increases, the Zener diode surrenders, the capacitance of the capacitor is added and the drain current and the drain voltage vary at a low speed, thereby suppressing the surge voltage low. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够同时抑制开关损耗和浪涌电压两者的开关电路。解决方案：本发明涉及一种通过切换晶体管的栅极电压来暂时切换导通状态和非导通状态之间的晶体管的主电极的开关电路，其中晶体管的漏极或集电极和其栅极或晶体管的漏极或集电极及其源极或发射极通过齐纳二极管和电容器的串联电路连接。当漏极电压低时，判定电容器的电容不由齐纳二极管贡献的状态，漏极电流和漏极电压以高速变化，从而降低开关损耗。当漏极电压增加时，齐纳二极管投降，电容器的电容被增加，漏极电流和漏极电压以低速度变化，从而抑制浪涌电压低。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2007019458A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007019458A
公开(公告)日：2007-01-25
申请号：JP2006046514
申请日：2006-02-23
申请人： Denso Corp , 株式会社デンソー
发明人： OZOE SHOJI , SHIGA TOMOHIDE , OKABE YOSHIFUMI , AOKI TAKAAKI , FUKAZAWA TAKESHI , KAYUKAWA KIMIJI
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/2855 , H01L21/76838 , H01L29/1095 , H01L29/456 , H01L29/66734
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which does not need to perform an annealing process without making the thickness of a silicon substrate thin, and to provide a method of manufacturing it.
SOLUTION: An Al film 10a is spattered to the rear surface of the silicon substrate 1 after grinding. Consequently, an amorphous silicon 11 formed at the time of grinding turns into a recrystallization silicon 12. Accordingly, the ohmic contact of the Al film 10a and the silicon substrate 1 is carried out, that is, it can carry out ohmic contact of the back electrode 10 and the silicon substrate 1. Therefore, a semiconductor device of the structure which does not need to perform annealing process without making the thickness of the silicon substrate thin.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供不需要进行退火处理而不使硅衬底的厚度变薄的半导体器件，并提供其制造方法。解决方案：研磨后，Al膜10a溅射到硅衬底1的后表面。因此，在研磨时形成的非晶硅11变成再结晶硅12.因此，进行Al膜10a和硅衬底1的欧姆接触，即可以进行背面的欧姆接触电极10和硅衬底1.因此，不需要在不使硅衬底的厚度变薄的情况下进行退火处理的结构的半导体器件。版权所有（C）2007，JPO＆INPIT

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