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    • 4. 发明专利
    • Semiconductor device and manufacturing method of the same
    • 半导体器件及其制造方法
    • JP2011029231A
    • 2011-02-10
    • JP2009170416
    • 2009-07-21
    • Denso CorpToyota Central R&D Labs Inc株式会社デンソー株式会社豊田中央研究所
    • HATTORI YOSHIKUNIKUWABARA MAKOTOTAGUCHI RIEMIZUNO SHOJISUMITOMO MASAKIYOOSAWA SEIGO
    • H01L29/78
    • PROBLEM TO BE SOLVED: To improve proof strength when a recovery current flows to a diode in which a switching semiconductor device exists. SOLUTION: The switching semiconductor device has a channel region 23a formed in the center in a range facing a surface of a semiconductor substrate, a resurf region RS1 formed in a peripheral part, a source region 25 formed in a range facing the surface of the channel region, a plurality of trench gate regions 21 and a conductive film FP 0 conducted to the gate region 21, and is formed on an insulating film. The trench regions 21 are arranged in parallel and ends in a longitudinal direction of a plurality of trenches are arranged on the same straight line. At least a part of the channel region projects out to a peripheral side of the semiconductor device rather than a straight line between adjacent pitches of a trench pair. The recovery current flows over a wide range of the channel region 23a and is not concentrated. COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:为了提高恢复电流流向存在开关半导体器件的二极管时的抗强度。 解决方案:切换半导体器件具有在面向半导体衬底的表面的范围内形成在中心的沟道区23a,形成在周边部分的再结晶区域RS1,形成在面向表面的范围内的源极区域25 沟道区域的多个沟槽栅极区域21和导电膜FP 0 传导到栅极区域21,并形成在绝缘膜上。 沟槽区域21平行布置并且在多个沟槽的纵向方向上的端部被布置在相同的直线上。 沟道区域的至少一部分突出到半导体器件的外围侧,而不是沟槽对的相邻间距之间的直线。 恢复电流在沟道区域23a的宽范围内流动并且不集中。 版权所有(C)2011,JPO&INPIT
    • 6. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2013235891A
    • 2013-11-21
    • JP2012106013
    • 2012-05-07
    • Denso Corp株式会社デンソー
    • KOYAMA KAZUHIROSUMITOMO MASAKIYOHIGUCHI YASUSHI
    • H01L29/739H01L29/78
    • H01L27/0722H01L27/0727H01L29/0834H01L29/1095H01L29/4236H01L29/7397H01L29/7827H01L29/861
    • PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing snap-back phenomenon, the conduction loss of an IGBT and an FWD, current concentration, and reduction in withstand voltage performance.SOLUTION: In a buffer layer 11, carrier density is set to be lower than spatial charge density. Thus, reduction in a resistance value can be suppressed even if the spatial discharge density of the buffer layer 11 is increased. Consequently, the resistance value of the buffer layer 11 can be made large even if a drift layer 2 is made thin for suppressing the conduction loss of an IGBT and the spatial charge density is increased for suppressing a depletion layer from reaching a collector layer 12. In other words, snap-back phenomenon can be suppressed while reducing the conduction loss of the IGBT, and further reduction in withstand voltage performance can be suppressed. Moreover, since there is no need to widen the width of the collector layer 12, increase in the conduction loss can be suppressed without reducing the effective area of the element, thereby suppressing current concentration.
    • 要解决的问题:提供一种能够抑制卡扣现象,IGBT的导通损耗和FWD,电流集中和耐压性能降低的半导体器件。解决方案:在缓冲层11中,设置载流子密度 低于空间电荷密度。 因此,即使缓冲层11的空间放电密度增加,也可以抑制电阻值的降低。 因此,即使为了抑制IGBT的导通损耗而使漂移层2变薄,并且为了抑制耗尽层到达集电极层12而增加空间电荷密度,可以使缓冲层11的电阻值变大。 换句话说,可以抑制回并现象,同时减少IGBT的导通损耗,并且可以抑制耐压性能的进一步降低。 此外,由于不需要扩大集电极层12的宽度,可以抑制导通损耗的增加,而不会降低元件的有效面积,从而抑制电流集中。
    • 7. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2013183071A
    • 2013-09-12
    • JP2012046618
    • 2012-03-02
    • Denso Corp株式会社デンソー
    • HIGUCHI YASUSHISUMITOMO MASAKIYO
    • H01L29/786H01L21/336H01L29/78
    • H01L29/7393H01L29/0808H01L29/1008H01L29/1095H01L29/4236H01L29/7394H01L29/7397H01L29/7824H01L29/7825
    • PROBLEM TO BE SOLVED: To suppress an increase in ON resistance and a decrease in breakdown tolerance, and further to suppress a decease in breakdown voltage.SOLUTION: A plurality of trenches 6 are formed reaching a reverse surface 2b of a drift layer 2, and a contact layer 5 is formed in a surface layer of the drift layer 2 on a tip end side in an extending direction of the plurality of trenches 6. When a predetermined voltage is applied to a gate electrode, a channel region is formed at a part of a base layer 3 which comes into contact with the trenches 6, and current flows along the trenches 6 in the extending direction of the trenches 6. Consequently, current never flows around to lower parts of the trenches 6, and even when a high voltage is applied at OFF time etc., generation of a high electric field at the lower parts of the trenches 6 can be suppressed. Consequently, an increase in ON resistance and a decrease in breakdown tolerance can be suppressed, and further a decrease in breakdown voltage can also be suppressed.
    • 要解决的问题:抑制导通电阻的增加和击穿耐受性的降低,进一步抑制击穿电压的下降。解决方案:形成多个沟槽6,到达漂移层2的背面2b,并且 在多个沟槽6的延伸方向的前端侧,在漂移层2的表面层上形成接触层5.当向栅电极施加预定电压时,在一部分形成沟道区 与沟槽6接触的基极层3的电流沿着沟槽6沿着沟槽6的延伸方向流动。因此,电流不会流到沟槽6的下部,并且即使当高电压 在OFF时间施加等,可以抑制在沟槽6的下部产生高电场。 因此,可以抑制导通电阻的增加和击穿耐受性的降低,并且还可以抑制击穿电压的降低。
    • 9. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2013084922A
    • 2013-05-09
    • JP2012196549
    • 2012-09-06
    • Denso Corp株式会社デンソー
    • HIGUCHI YASUSHISUMITOMO MASAKIYOFUKATSU SHIGEMITSU
    • H01L29/78H01L29/739
    • H01L29/7397H01L29/0834H01L29/0843H01L29/1095H01L29/4236H01L29/42368H01L29/42376H01L29/66348
    • PROBLEM TO BE SOLVED: To improve short-circuit withstanding capability while achieving low on-state voltage.SOLUTION: A semiconductor device comprises a trench gate having a bottom part in a drift layer and including a communication part formed to communicate from a surface of a base layer to the bottom part. The communication part is formed, with respect to a x-y plane defined by an x direction and a y direction orthogonal to each other and a z direction orthogonal to the x-y plane, from a surface of the base layer along the x-y plane to a depth of a distance D1 in the z direction, and the bottom part is formed from a connection surface with the communication part to a depth of a distance D2 in the z direction. The trench gate extends in the y direction and has a width in the x direction at the bottom part is larger than a width of the communication part. Further, a region between neighboring trench gates has an effective region corresponding to an emitter layer that serves as an injection source of charge to the drift layer, and an ineffective region that generates no injection source of charge. The effective regions are separated at a distance Lin the y direction. The distance Lof the effective region satisfies a relationship represented as L≤2(D+D).
    • 要解决的问题:提高短路耐受能力,同时实现低导通电压。 解决方案:半导体器件包括沟槽栅极,沟槽栅极在漂移层中具有底部,并且包括形成为从基底层的表面到底部部分的连通的连通部。 通信部分相对于从xy平面垂直的x方向和ay方向和xy方向定义的xy平面形成,从基底层的沿xy平面的表面延伸到距离的深度 D1在z方向上,并且底部由与连通部的连接表面形成为在z方向上的距离D2的深度。 沟槽栅极沿y方向延伸,并且在底部的x方向上的宽度大于连通部的宽度。 此外,相邻沟槽栅极之间的区域具有对应于用作向漂移层的注入电荷源的发射极层的有效区域和不产生注入电荷源的无效区域。 有效区域在y方向上以距离L 1 分开。 有效区域的距离L 1 满足表示为L 1 ≤2的关系(D 1 + D 2 )。 版权所有(C)2013,JPO&INPIT
    • 10. 发明专利
    • Semiconductor device
    • 半导体器件
    • JP2012080074A
    • 2012-04-19
    • JP2011145461
    • 2011-06-30
    • Denso Corp株式会社デンソー
    • SUMITOMO MASAKIYOHIGUCHI YASUSHIFUKATSU SHIGEMITSU
    • H01L29/78H01L21/336
    • H01L29/7397H01L29/0619H01L29/0834H01L29/0839H01L29/1095H01L29/4236H01L29/66348
    • PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving a load short-circuit withstand capability while achieving low on-resistance, and to provide a method of manufacturing the same.SOLUTION: Trench gates 8 include bottom portions protruding in the direction parallel to a main surface of a collector layer 1, which is the direction perpendicular to the extending direction of trenches 5, in a drift layer 3. The distance between the bottom portions of the adjacent trench gates 8 is set to be shorter than the distance between the portions opposite to the bottom portions of the adjacent trench gates 8. Additionally, in the trenches 5, the thickness of gate insulating films 6 provided on the wall surfaces constituting the bottom portions is set to be thicker than that of the gate insulating films 6 provided on the wall surfaces closer to the opening sides than the wall surfaces constituting the bottom portions.
    • 要解决的问题:提供能够在实现低导通电阻的同时提高负载短路耐受能力的半导体器件,并提供其制造方法。 解决方案:沟槽门8包括在漂移层3中沿与沟槽5的延伸方向垂直的方向平行于集电体层1的主表面的方向突出的底部。底部之间的距离 相邻的沟槽栅极8的部分被设定为比相邻的沟槽栅8的底部相反的部分之间的距离短。另外,在沟槽5中,设置在构成的壁面上的栅极绝缘膜6的厚度 将底部设定为比构成底部的壁面更靠近开口侧的壁面上的栅极绝缘膜6的厚度设定为较厚。 版权所有(C)2012,JPO&INPIT