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1. 发明申请

US20130153964A1 FETs with Hybrid Channel Materials 有权
标题翻译：混合通道材料的FET
公开(公告)号：US20130153964A1
公开(公告)日：2013-06-20
申请号：US13326825
申请日：2011-12-15
申请人： Dechao Guo , Shu-Jen Han , Edward William Kiewra , Kuen-Ting Shiu
发明人： Dechao Guo , Shu-Jen Han , Edward William Kiewra , Kuen-Ting Shiu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/8258 , H01L21/823807 , H01L27/0605
摘要： Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.
摘要翻译：提供在同一CMOS电路内采用不同通道材料的技术。一方面，制造CMOS电路的方法包括以下步骤。提供了在绝缘体上具有第一半导体层的晶片。 STI用于将第一半导体层分成第一有源区和第二有源区。第一半导体层凹入第一有源区。第二半导体层在第一半导体层上外延生长，其中第二半导体层包括具有至少一个III族元素和至少一个V族元素的材料。使用第二半导体层作为n-FET的沟道材料，在第一有源区中形成n-FET。使用第一半导体层作为p-FET的沟道材料，在第二有源区中形成p-FET。

2. 发明授权

US08610172B2 FETs with hybrid channel materials 有权
标题翻译：具有混合通道材料的FET
公开(公告)号：US08610172B2
公开(公告)日：2013-12-17
申请号：US13326825
申请日：2011-12-15
申请人： Dechao Guo , Shu-Jen Han , Edward William Kiewra , Kuen-Ting Shiu
发明人： Dechao Guo , Shu-Jen Han , Edward William Kiewra , Kuen-Ting Shiu
IPC分类号： H01L29/66
CPC分类号： H01L21/8258 , H01L21/823807 , H01L27/0605
摘要： Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.
摘要翻译：提供在同一CMOS电路内采用不同通道材料的技术。一方面，制造CMOS电路的方法包括以下步骤。提供了在绝缘体上具有第一半导体层的晶片。 STI用于将第一半导体层分成第一有源区和第二有源区。第一半导体层凹入第一有源区。第二半导体层在第一半导体层上外延生长，其中第二半导体层包括具有至少一个III族元素和至少一个V族元素的材料。使用第二半导体层作为n-FET的沟道材料，在第一有源区中形成n-FET。使用第一半导体层作为p-FET的沟道材料，在第二有源区中形成p-FET。

3. 发明申请

US20120187505A1 Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation 审中-公开
标题翻译：自对准III-V MOSFET制造，具有原位III-V外延和原位金属外延和接触形成
公开(公告)号：US20120187505A1
公开(公告)日：2012-07-26
申请号：US13013206
申请日：2011-01-25
申请人： Dechao Guo , Shu-Jen Han , Jeehwan Kim , Kuen-Ting Shiu
发明人： Dechao Guo , Shu-Jen Han , Jeehwan Kim , Kuen-Ting Shiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/8252 , H01L21/26546 , H01L21/28575 , H01L21/3245 , H01L29/0847 , H01L29/201 , H01L29/207 , H01L29/41783 , H01L29/452 , H01L29/66446 , H01L29/66477 , H01L29/66522 , H01L29/66628 , H01L29/78
摘要： A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.
摘要翻译：一种用于形成晶体管的方法，包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物与源/漏区相邻形成的区域。该方法包括在源极/漏极区域上生长凸起的源极/漏极区域，生长的升高的源极/漏极区域包括III-V半导体材料，以及在生长的升高的源极/漏极区域上生长的金属接触。形成晶体管的另一种方法包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物与源/漏区相邻形成的区域。该方法包括在源/漏区上生长金属接触。还公开了晶体管和计算机程序产品。

4. 发明授权

US08524614B2 III-V compound semiconductor material passivation with crystalline interlayer 有权
标题翻译： III-V化合物半导体材料钝化与晶体中间层
公开(公告)号：US08524614B2
公开(公告)日：2013-09-03
申请号：US12955203
申请日：2010-11-29
申请人： Kuen-Ting Shiu , Dechao Guo , Shu-Jen Han , Edward W. Kiewra , Masaharu Kobayashi
发明人： Kuen-Ting Shiu , Dechao Guo , Shu-Jen Han , Edward W. Kiewra , Masaharu Kobayashi
IPC分类号： H01L21/31
CPC分类号： H01L29/0603 , H01L21/28158 , H01L21/28264 , H01L29/517 , H01L29/66522 , H01L29/78 , H01L29/7833
摘要： The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.
摘要翻译：本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。

5. 发明申请

US20130175633A1 CONTROLLING THRESHOLD VOLTAGE IN CARBON BASED FIELD EFFECT TRANSISTORS 失效
标题翻译：基于碳的场效应晶体管控制阈值电压
公开(公告)号：US20130175633A1
公开(公告)日：2013-07-11
申请号：US13607589
申请日：2012-09-07
申请人： Martin M. Frank , Dechao Guo , Shu-Jen Han , Kuen-Ting Shiu
发明人： Martin M. Frank , Dechao Guo , Shu-Jen Han , Kuen-Ting Shiu
IPC分类号： H01L27/092
CPC分类号： H01L51/0048 , B82Y10/00 , H01L21/823807 , H01L21/823828 , H01L27/1203 , H01L29/413 , H01L51/0558
摘要： A field effect transistor fabrication method includes defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure.
摘要翻译：场效应晶体管制造方法包括：在衬底上限定栅极结构，在栅极结构上沉积介电层，在介电层上沉积第一金属层，去除第一金属层的一部分，沉积第二金属层，退火第一和第二金属层，并且在电介质层和栅极结构上限定碳基器件。

6. 发明申请

US20120132913A1 III-V Compound Semiconductor Material Passivation With Crystalline Interlayer 有权
标题翻译： III-V复合半导体材料钝化与结晶中间层
公开(公告)号：US20120132913A1
公开(公告)日：2012-05-31
申请号：US12955203
申请日：2010-11-29
申请人： Kuen-Ting Shiu , Dechao Guo , Shu-Jen Han , Edward W. Kiewra , Masaharu Kobayashi
发明人： Kuen-Ting Shiu , Dechao Guo , Shu-Jen Han , Edward W. Kiewra , Masaharu Kobayashi
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/0603 , H01L21/28158 , H01L21/28264 , H01L29/517 , H01L29/66522 , H01L29/78 , H01L29/7833
摘要： The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.
摘要翻译：本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。

7. 发明授权

US08420474B1 Controlling threshold voltage in carbon based field effect transistors 失效
公开(公告)号：US08420474B1
公开(公告)日：2013-04-16
申请号：US13348355
申请日：2012-01-11
申请人： Martin M. Frank , Dechao Guo , Shu-Jen Hen , Kuen-Ting Shiu
发明人： Martin M. Frank , Dechao Guo , Shu-Jen Hen , Kuen-Ting Shiu
IPC分类号： H01L21/8238
CPC分类号： H01L51/0048 , B82Y10/00 , H01L21/823807 , H01L21/823828 , H01L27/1203 , H01L29/413 , H01L51/0558
摘要： A field effect transistor fabrication method includes defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure.

8. 发明授权

US08598665B2 Controlling threshold voltage in carbon based field effect transistors 失效
标题翻译：控制基于碳的场效应晶体管的阈值电压
公开(公告)号：US08598665B2
公开(公告)日：2013-12-03
申请号：US13607589
申请日：2012-09-07
申请人： Martin M. Frank , Dechao Guo , Shu-Jen Hen , Kuen-Ting Shiu
发明人： Martin M. Frank , Dechao Guo , Shu-Jen Hen , Kuen-Ting Shiu
IPC分类号： H01L27/01
CPC分类号： H01L51/0048 , B82Y10/00 , H01L21/823807 , H01L21/823828 , H01L27/1203 , H01L29/413 , H01L51/0558
摘要： A field effect transistor fabrication method includes defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure.
摘要翻译：场效应晶体管制造方法包括：在衬底上限定栅极结构，在栅极结构上沉积介电层，在介电层上沉积第一金属层，去除第一金属层的一部分，沉积第二金属层，退火第一和第二金属层，并且在电介质层和栅极结构上限定碳基器件。

9. 发明授权

US08742475B2 Field effect transistor device and fabrication 有权
标题翻译：场效应晶体管器件和制造
公开(公告)号：US08742475B2
公开(公告)日：2014-06-03
申请号：US13554294
申请日：2012-07-20
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/42368 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L29/66477
摘要： In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.
摘要翻译：在本发明的一个方面中，场效应晶体管（FET）器件包括：第一FET，其包括设置在基板上的电介质层，设置在电介质层上的第一金属层的第一部分和设置在电介质层上的第二金属层第一金属层，包括设置在电介质层上的第一金属层的第二部分的第二FET以及将第一FET与第二FET分离的边界区域。

10. 发明授权

US08519454B2 Structure and process for metal fill in replacement metal gate integration 有权
标题翻译：金属填充金属栅极整合的结构和工艺
公开(公告)号：US08519454B2
公开(公告)日：2013-08-27
申请号：US13075443
申请日：2011-03-30
申请人： Dechao Guo , Shu-Jen Han , Keith Kwong Hon Wong , Jun Yuan
发明人： Dechao Guo , Shu-Jen Han , Keith Kwong Hon Wong , Jun Yuan
IPC分类号： H01L29/76 , H01L21/338 , H01L21/84
CPC分类号： H01L29/4966 , H01L29/66545 , H01L29/7843
摘要： Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack.
摘要翻译：本文提供了用于替换金属栅极集成方案和所得器件的金属填充工艺。该方法包括在半导体衬底上形成虚拟栅极。虚拟门包括在第一材料和第二材料之间形成金属层。该方法还包括部分地去除伪栅极以形成由间隔物材料限定的开口。该方法还包括在间隔物材料中形成凹槽以加宽开口的一部分。该方法还包括通过开口去除虚拟栅极的剩余部分以形成具有形成其上部的凹部的沟槽。该方法还包括用替换的金属栅极堆叠填充沟槽和凹部。

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