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1. 发明申请

US20110320735A1 DYNAMICALLY ALTERING A PIPELINE CONTROLLER MODE BASED ON RESOURCE AVAILABILITY 失效
标题翻译：基于资源可用性动态地改变管道控制器模式
公开(公告)号：US20110320735A1
公开(公告)日：2011-12-29
申请号：US12821766
申请日：2010-06-23
申请人： Deanna Postles Dunn Berger , Michael Fee , Kenneth D. Klapproth , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael Fee , Kenneth D. Klapproth , Robert J. Sonnelitter, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F12/0811 , G06F12/0851 , G06F12/0857
摘要： A mechanism for dynamically altering a request received at a hardware component is provided. The request is received at the hardware component, and the request includes a mode option. It is determined whether an action of the request requires an unavailable resource and it is determined whether the mode option is for the action requiring the unavailable resource. In response to the mode option being for the action requiring the unavailable resource, the action is automatically removed from the request. The request is passed for pipeline arbitration without the action requiring the unavailable resource.
摘要翻译：提供了用于动态地改变在硬件组件处接收到的请求的机制。该请求在硬件组件处被接收，该请求包括模式选项。确定请求的动作是否需要不可用资源，并且确定模式选项是否用于需要不可用资源的动作。响应于要求不可用资源的操作的模式选项，该操作将自动从请求中移除。该请求被传递用于流水线仲裁，而不需要不可用资源的动作。

2. 发明授权

US08639887B2 Dynamically altering a pipeline controller mode based on resource availability 失效
标题翻译：基于资源可用性动态更改流水线控制器模式
公开(公告)号：US08639887B2
公开(公告)日：2014-01-28
申请号：US12821766
申请日：2010-06-23
申请人： Deanna Postles Dunn Berger , Michael Fee , Kenneth D. Klapproth , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael Fee , Kenneth D. Klapproth , Robert J. Sonnelitter, III
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0855 , G06F12/0811 , G06F12/0851 , G06F12/0857
摘要： A mechanism for dynamically altering a request received at a hardware component is provided. The request is received at the hardware component, and the request includes a mode option. It is determined whether an action of the request requires an unavailable resource and it is determined whether the mode option is for the action requiring the unavailable resource. In response to the mode option being for the action requiring the unavailable resource, the action is automatically removed from the request. The request is passed for pipeline arbitration without the action requiring the unavailable resource.
摘要翻译：提供了用于动态地改变在硬件组件处接收到的请求的机制。该请求在硬件组件处被接收，该请求包括模式选项。确定请求的动作是否需要不可用资源，并且确定模式选项是否用于需要不可用资源的动作。响应于要求不可用资源的操作的模式选项，该操作将自动从请求中移除。该请求被传递用于流水线仲裁，而不需要不可用资源的动作。

3. 发明授权

US08635409B2 Dynamic mode transitions for cache instructions 失效
标题翻译：高速缓存指令的动态模式转换
公开(公告)号：US08635409B2
公开(公告)日：2014-01-21
申请号：US12821706
申请日：2010-06-23
申请人： Deanna Postles Dunn Berger , Michael F. Fee , Kenneth D. Klapproth , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael F. Fee , Kenneth D. Klapproth , Robert J. Sonnelitter, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F12/0811 , G06F12/084 , G06F12/0846
摘要： A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter; selecting one of the plurality of requests as a selected request the selected request having been provided by a first state machine; determining that the selected request includes a mode that requires a first step and a second step, the first step including an access to a location in a cache; determining that the location in the cache is unavailable; and replacing the mode with a modified mode that only includes the second step.
摘要翻译：向缓存流水线提供请求的方法包括：从仲裁器的一个或多个状态机接收多个请求; 从所选择的请求中选择所述多个请求中的一个请求，所述请求已由第一状态机提供; 确定所选择的请求包括需要第一步骤和第二步骤的模式，所述第一步骤包括对高速缓存中的位置的访问; 确定高速缓存中的位置不可用; 并用仅包括第二步的修改模式替换该模式。

4. 发明申请

US20110320725A1 DYNAMIC MODE TRANSITIONS FOR CACHE INSTRUCTIONS 失效
标题翻译：缓存指令的动态模式转换
公开(公告)号：US20110320725A1
公开(公告)日：2011-12-29
申请号：US12821706
申请日：2010-06-23
申请人： Deanna Postles Dunn Berger , Michael F. Fee , Kenneth D. Klapproth , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael F. Fee , Kenneth D. Klapproth , Robert J. Sonnelitter, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F12/0811 , G06F12/084 , G06F12/0846
摘要： A method of providing requests to a cache pipeline includes receiving a plurality of requests from one or more state machines at an arbiter, selecting one of the plurality of requests as a selected request, the selected request having been provided by a first state machine, determining that the selected request includes a mode that requires a first step and a second step, the first step including an access to a location in a cache, determining that the location in the cache is unavailable, and replacing the mode with a modified mode that only includes the second step.
摘要翻译：向高速缓存流水线提供请求的方法包括：从仲裁器的一个或多个状态机接收多个请求，将所述多个请求中的一个请求选择为所选择的请求，所选择的请求由第一状态机提供，确定所选择的请求包括需要第一步骤和第二步骤的模式，第一步骤包括对高速缓存中的位置的访问，确定高速缓存中的位置不可用，并且以仅修改模式替换模式包括第二步。

5. 发明授权

US08478920B2 Controlling data stream interruptions on a shared interface 失效
标题翻译：控制共享接口上的数据流中断
公开(公告)号：US08478920B2
公开(公告)日：2013-07-02
申请号：US12822333
申请日：2010-06-24
申请人： Garrett M. Drapala , Kenneth D. Klapproth , Robert J. Sonnelitter, III , Craig R. Walters
发明人： Garrett M. Drapala , Kenneth D. Klapproth , Robert J. Sonnelitter, III , Craig R. Walters
IPC分类号： G06F13/00
CPC分类号： G06F13/26
摘要： A mechanism for controlling data stream interruptions on a shared bus is provided. A first request is received to transfer data. High priority data components and low priority data components are determined for the first request. The high priority data components are transferred without interruptions. In response to receiving requests when transferring the high priority data components, the received requests are rejected.
摘要翻译：提供了一种用于控制共享总线上的数据流中断的机制。接收到第一个要求来传输数据。为第一个请求确定高优先级数据组件和低优先级数据组件。高优先级数据组件无间断地传输。响应于在传送高优先级数据组件时的接收请求，接收到的请求被拒绝。

6. 发明申请

US20110320657A1 CONTROLLING DATA STREAM INTERRUPTIONS ON A SHARED INTERFACE 失效
标题翻译：控制分布式接口上的数据流中断
公开(公告)号：US20110320657A1
公开(公告)日：2011-12-29
申请号：US12822333
申请日：2010-06-24
申请人： Garrett M. Drapala , Kenneth D. Klapproth , Robert J. Sonnelitter, III , Craig R. Walters
发明人： Garrett M. Drapala , Kenneth D. Klapproth , Robert J. Sonnelitter, III , Craig R. Walters
IPC分类号： G06F13/36
CPC分类号： G06F13/26
摘要： A mechanism for controlling data stream interruptions on a shared bus is provided. A first request is received to transfer data. High priority data components and low priority data components are determined for the first request. The high priority data components are transferred without interruptions. In response to receiving requests when transferring the high priority data components, the received requests are rejected.
摘要翻译：提供了一种用于控制共享总线上的数据流中断的机制。接收到第一个要求来传输数据。为第一个请求确定高优先级数据组件和低优先级数据组件。高优先级数据组件无间断地传输。响应于在传送高优先级数据组件时的接收请求，接收到的请求被拒绝。

7. 发明授权

US08990507B2 Storing data in a system memory for a subsequent cache flush 有权
公开(公告)号：US08990507B2
公开(公告)日：2015-03-24
申请号：US13495383
申请日：2012-06-13
申请人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
发明人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0895 , G06F12/0804 , G06F12/0817 , G06F12/0891 , G06F12/128
摘要： Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.

8. 发明申请

US20110320700A1 Concurrent Refresh In Cache Memory 失效
标题翻译：缓存中并发刷新
公开(公告)号：US20110320700A1
公开(公告)日：2011-12-29
申请号：US12822364
申请日：2010-06-24
申请人： Timothy C. Bronson , Hieu T. Huynh , Charlie C. Hwang , Kenneth D. Klapproth
发明人： Timothy C. Bronson , Hieu T. Huynh , Charlie C. Hwang , Kenneth D. Klapproth
IPC分类号： G06F12/06
CPC分类号： G06F12/0846 , G06F12/0893
摘要： Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of the cache memory, transmitting a starting time of the refresh time interval to a bank controller, the bank controller being local to, and associated with, only one cache memory bank of the cache memory, sampling a continuous refresh status indicative of a number of refreshes necessary to maintain data within the cache memory bank associated with the bank controller, requesting a gap in a processing pipeline of the cache memory to facilitate the number of refreshes necessary, receiving a refresh grant in response to the requesting, and transmitting an encoded refresh command to the bank controller, the encoded refresh command indicating a number of refresh operations granted to the cache memory bank associated with the bank controller.
摘要翻译：高速缓冲存储器中的并发刷新包括计算集中式刷新控制器的刷新时间间隔，集中式刷新控制器对于高速缓存存储器的所有高速缓存存储体共同，将刷新时间间隔的开始时间发送到银行控制器，银行控制器本身并且仅与高速缓冲存储器的一个高速缓冲存储器组相关联，并且对与表示控制器相关联的高速缓存存储器中的数据进行维护所需的刷新次数的连续刷新状态进行采样，请求在处理高速缓冲存储器的流水线以便于所需的刷新次数，响应于请求接收刷新许可，并向编组控制器发送编码的刷新命令，编码的刷新命令指示授予高速缓冲存储器的刷新操作的次数与银行控制人有关的银行。

9. 发明申请

US20110320699A1 System Refresh in Cache Memory 审中-公开
标题翻译：缓存内存中的系统刷新
公开(公告)号：US20110320699A1
公开(公告)日：2011-12-29
申请号：US12822361
申请日：2010-06-24
申请人： Michael Blake , Timothy Bronson , Hieu Huynh , Kenneth D. Klapproth
发明人： Michael Blake , Timothy Bronson , Hieu Huynh , Kenneth D. Klapproth
IPC分类号： G06F12/08 , G06F1/04 , G06F12/00
CPC分类号： G06F12/0897 , G06F13/14 , G06F13/16 , G06F13/1605 , G06F13/1636 , G11C11/406 , G11C11/40603 , G11C11/40607 , G11C11/40618
摘要： System refresh in a cache memory includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory, activating a refresh request at the centralized refresh controller in response to generating the RTIM pulse, the refresh request associated with a single cache memory bank of the cache memory, receiving a refresh grant in response to activating the refresh request, and transmitting the refresh grant to a bank controller, the bank controller associated, and localized, at the single cache memory bank of the cache memory.
摘要翻译：高速缓冲存储器中的系统刷新包括在高速缓存存储器的集中式刷新控制器处产生刷新时间周期（RTIM）脉冲，响应于产生RTIM脉冲在集中式刷新控制器处激活刷新请求，刷新请求与单个高速缓冲存储器的高速缓冲存储器组，响应于激活刷新请求而接收刷新许可，以及将刷新许可发送到在高速缓存存储器的单个高速缓冲存储器组处相关联并被本地化的存储体控制器。

10. 发明授权

US08458405B2 Cache bank modeling with variable access and busy times 失效
标题翻译：缓存库建模与可变访问和繁忙时间
公开(公告)号：US08458405B2
公开(公告)日：2013-06-04
申请号：US12821891
申请日：2010-06-23
申请人： Timothy C. Bronson , Garrett M. Drapala , Hieu T. Huynh , Kenneth D. Klapproth
发明人： Timothy C. Bronson , Garrett M. Drapala , Hieu T. Huynh , Kenneth D. Klapproth
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0895
摘要： Various embodiments of the present invention manage access to a cache memory. In one embodiment, a set of cache bank availability vectors are generated based on a current set of cache access requests currently operating on a set of cache banks and at least a variable busy time of a cache memory includes the set of cache banks. The set of cache bank availability vectors indicate an availability of the set of cache banks. A set of cache access requests for accessing a set of given cache banks within the set of cache banks is received. At least one cache access request in the set of cache access requests is selected to access a given cache bank based on the a cache bank availability vectors associated with the given cache bank and the set of access request parameters associated with the at least one cache access that has been selected.
摘要翻译：本发明的各种实施例管理对高速缓冲存储器的访问。在一个实施例中，基于当前在一组高速缓存组上操作的当前高速缓存访问请求集合来生成一组高速缓存存储库可用性向量，并且至少高速缓冲存储器的可变繁忙时间包括该组缓存存储体。该组缓存库可用性向量指示该组缓存存储体的可用性。接收用于访问该组缓存组内的一组给定高速缓存存储体的一组缓存访问请求。选择该组高速缓存访问请求中的至少一个高速缓存访问请求以基于与给定高速缓存组相关联的高速缓存存储体可用性向量和与该至少一个高速缓存访问相关联的一组访问请求参数访问给定高速缓存组已被选中。

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