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1. 发明申请

US20090199139A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR IMPROVED ELECTRICAL ANALYSIS 有权
标题翻译：用于改进电气分析的方法，系统和计算机程序产品
公开(公告)号：US20090199139A1
公开(公告)日：2009-08-06
申请号：US12344327
申请日：2008-12-26
申请人： David White , Matthew Liberty , Eric Nequist , Michael McSherry
发明人： David White , Matthew Liberty , Eric Nequist , Michael McSherry
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An improved method, system, user interface, and computer program product is described for using a memory and learning component to improve capacitance and resistance estimates based on the types of layouts and devices being evaluated. According to some approaches, a learning component is implemented that uses recommended test sets from the evaluation component to automatically test the extraction estimates against the field solver. Variability models from manufacturing or electrical analysis may also be used to select a series of objects (unique conductor geometries) that make up a conduction path or net or specific conductor geometries for evaluation and additional learning improvement.
摘要翻译：描述了一种改进的方法，系统，用户界面和计算机程序产品，用于使用存储器和学习组件，以根据正在评估的布局和设备的类型来改进电容和电阻估计。根据一些方法，实现了使用来自评估组件的推荐测试集来自动测试针对场解算器的提取估计的学习组件。还可以使用来自制造或电气分析的变量模型来选择构成传导路径或网络或特定导体几何形状以用于评估和额外学习改进的一系列物体（独特的导体几何形状）。

2. 发明授权

US08386975B2 Method, system, and computer program product for improved electrical analysis 有权
标题翻译：方法，系统和计算机程序产品，用于改进电气分析
公开(公告)号：US08386975B2
公开(公告)日：2013-02-26
申请号：US12344327
申请日：2008-12-26
申请人： David White , Matthew Liberty , Eric Nequist , Michael McSherry
发明人： David White , Matthew Liberty , Eric Nequist , Michael McSherry
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An improved method, system, user interface, and computer program product is described for using a memory and learning component to improve capacitance and resistance estimates based on the types of layouts and devices being evaluated. According to some approaches, a learning component is implemented that uses recommended test sets from the evaluation component to automatically test the extraction estimates against the field solver. Variability models from manufacturing or electrical analysis may also be used to select a series of objects (unique conductor geometries) that make up a conduction path or net or specific conductor geometries for evaluation and additional learning improvement.
摘要翻译：描述了一种改进的方法，系统，用户界面和计算机程序产品，用于使用存储器和学习组件，以根据正在评估的布局和设备的类型来改进电容和电阻估计。根据一些方法，实现了使用来自评估组件的推荐测试集来自动测试针对场解算器的提取估计的学习组件。还可以使用来自制造或电气分析的变量模型来选择构成传导路径或网络或特定导体几何形状以用于评估和额外学习改进的一系列物体（独特的导体几何形状）。

3. 发明授权

US08694950B2 Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness 有权
标题翻译：实现具有电气意识的电子电路设计的方法，系统和制造
公开(公告)号：US08694950B2
公开(公告)日：2014-04-08
申请号：US12982721
申请日：2010-12-30
申请人： Michael McSherry , David White , Ed Fischer , Bruce Yanagida , Prakash Gopalakrishnan , Keith Dennison , Akshat Shah
发明人： Michael McSherry , David White , Ed Fischer , Bruce Yanagida , Prakash Gopalakrishnan , Keith Dennison , Akshat Shah
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness.
摘要翻译：公开了一种用于实现具有电气意识的电子电路设计的方法，系统和计算机程序产品。该方法或系统使用电寄生数据或与电寄生相关联的电特性数据来更新原理图级别工具和物理设计工具，因此原理图和物理设计工具都可以了解执行中的电子寄生或特征数据它们的功能如基于抽取的模拟。方法或系统在实现或创建少于完整布局的部分布局时也会意识到EM或IR-drop约束。该方法或系统还提供用于设计工具的用户界面，以提供用于实现具有电气意识的电子电路设计的原位，可定制的实时信息。方法或系统还支持电气电路设计实现的约束验证，具有电气意识。

4. 发明授权

US08782577B2 Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness 有权
标题翻译：在设计具有电气意识的电子电路时提供原位可定制的信息的方法，装置和制造
公开(公告)号：US08782577B2
公开(公告)日：2014-07-15
申请号：US12982822
申请日：2010-12-30
申请人： Ed Fischer , David White , Michael McSherry , Bruce Yanagida , Vance Kenzle
发明人： Ed Fischer , David White , Michael McSherry , Bruce Yanagida , Vance Kenzle
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation.
摘要翻译：公开了一种用于在设计具有电气意识的电子电路中提供可定制信息的方法，系统和计算机程序产品。该方法或系统在第一显示区域中显示电子电路的物理设计的一部分。该方法或系统接收或识别用户或系统对电子电路的物理设计的部分的操纵。该方法或系统然后确定并显示对第一显示区域中的操纵的原位响应。该方法或系统可以在第一显示区域或另一显示区域中进一步显示与部件的物理数据有关的结果，与物理数据相关的电子寄生（一个或多个），相关联的电特性与物理设计的物理数据或电特性或其他元素的物理设计受到操纵的影响。

5. 发明授权

US09330222B2 Methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness 有权
标题翻译：用于实现具有电迁移意识的电子电路设计的方法，系统和制造
公开(公告)号：US09330222B2
公开(公告)日：2016-05-03
申请号：US12982762
申请日：2010-12-30
申请人： David White , Michael McSherry , Ed Fischer , Bruce Yanagida , Prakash Gopalakrishnan
发明人： David White , Michael McSherry , Ed Fischer , Bruce Yanagida , Prakash Gopalakrishnan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the EM related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.
摘要翻译：公开了用于实现具有电迁移意识的电子电路设计的方法，系统和制造。一些实施例执行示意性级仿真以确定电特性，识别布局组件的物理寄生效应，确定与组件上的电迁移分析相关联的电或物理特性，并且确定该组件是否满足EM相关约束同时在一些实施例中实现电子电路的物理设计。一些实施例进一步确定对于不符合EM相关约束的组件或相关数据的调整和/或以提示的形式呈现调整。各种数据和信息，例如各种形式或电压的电流，在各种示意图级别的工具和物理级别工具之间传递。

6. 发明授权

US08762914B2 Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness 有权
标题翻译：用于实现具有电气意识的电子电路设计的约束验证的方法，系统和制造
公开(公告)号：US08762914B2
公开(公告)日：2014-06-24
申请号：US12982732
申请日：2010-12-30
申请人： Ed Fischer , Michael McSherry , David White , Bruce Yanagida , Akshat Shah
发明人： Ed Fischer , Michael McSherry , David White , Bruce Yanagida , Akshat Shah
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied. Some embodiments further map schematic level parasitic constraints to a physical design representation and then compares the mapped parasitic constraints with corresponding electrical constraints to determine whether the mapped constraints are met.
摘要翻译：公开了用于实现具有电气意识的电子电路设计的约束验证的方法，系统和制造。一些实施例识别或设置寄生约束，并将电子寄生与相应的寄生约束进行比较，以确定是否满足寄生约束。一些实施例首先识别，确定或更新部分布局的部件的物理数据，并表征与部件的物理数据相关联的电寄生效应。一些实施例基于示意性模拟结果和性能约束来识别或确定一些示意图级性能约束并且估计寄生约束; 然后将估计的寄生约束与相应的电寄生效应进行比较，以确定是否满足约束。一些实施例还将原理层级寄生约束映射到物理设计表示，然后将映射的寄生约束与对应的电限制进行比较，以确定是否满足映射的约束。

7. 发明授权

US08701067B1 Methods, systems, and articles of manufactures for implementing electronic circuit designs with IR-drop awareness 有权
标题翻译：用于实现具有IR-drop意识的电子电路设计的制造方法，系统和制品
公开(公告)号：US08701067B1
公开(公告)日：2014-04-15
申请号：US13189274
申请日：2011-07-22
申请人： Michael McSherry , Bruce Yanagida , Ed Fischer , David White , Prakash Krishnan
发明人： Michael McSherry , Bruce Yanagida , Ed Fischer , David White , Prakash Krishnan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are a method, system, and computer program product for implementing electronic circuit designs with IR-drop awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to IR-drop analysis on the component, and determines whether the component meets IR-drop related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the IR-drop related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.
摘要翻译：公开了一种用于实现具有IR-drop意识的电子电路设计的方法，系统和计算机程序产品。一些实施例执行示意性级仿真以确定电特性，识别布局组件的物理寄生效应，确定与组件上的IR降分析相关联的电或物理特性，并确定该组件是否满足IR-丢弃相关约束同时在一些实施例中实现电子电路的物理设计。一些实施例进一步确定对组件或相关数据的调整，其中不涉及IR-滴相关的约束和/或以提示的形式呈现调整。各种数据和信息，例如各种形式或电压的电流，在各种示意图级别的工具和物理级别工具之间传递。

8. 发明授权

US08694933B2 Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness 有权
标题翻译：用于实现具有仿真意识的电子电路设计的方法，系统和制造
公开(公告)号：US08694933B2
公开(公告)日：2014-04-08
申请号：US12982790
申请日：2010-12-30
申请人： Prakash Gopalakrishnan , Michael McSherry , David White , Ed Fischer , Bruce Yanagida , Keith Dennison
发明人： Prakash Gopalakrishnan , Michael McSherry , David White , Ed Fischer , Bruce Yanagida , Keith Dennison
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.
摘要翻译：公开了实现具有模拟意识的电子设计的方法，系统和制造。在原理图级别识别或创建和模拟原理图，以表征电路的功能特性或确保电路设计符合要求的设计规范。识别，创建或更新设计组件的物理数据，并对与物理数据相关的电子寄存进行表征。与寄生相关联的一个或多个电特性被进一步表征并映射到仿真器以重新模拟电路设计以分析寄生效应的影响。一些实施例通过接受来自设计环境的增量设计或参数改变以交互方式递增地重新运行相同的模拟过程。

9. 发明授权

US08689169B2 Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness 有权
公开(公告)号：US08689169B2
公开(公告)日：2014-04-01
申请号：US12982628
申请日：2010-12-30
申请人： Ed Fischer , David White , Michael McSherry , Bruce Yanagida
发明人： Ed Fischer , David White , Michael McSherry , Bruce Yanagida
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , G06F17/5077
摘要： Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation.

10. 发明申请

US20080133569A1 SYSTEM AND METHOD FOR CONTENT HANDLING AND BUNDLING FOR MOBILE HANDSET DEVICE 审中-公开
标题翻译：用于移动手机装置的内容处理和装配的系统和方法
公开(公告)号：US20080133569A1
公开(公告)日：2008-06-05
申请号：US11566110
申请日：2006-12-01
申请人： Vincent Vu , Kiyoto Hirai , Seth Cummings , Michael McSherry
发明人： Vincent Vu , Kiyoto Hirai , Seth Cummings , Michael McSherry
IPC分类号： G06F17/30
CPC分类号： H04N21/235 , G06Q30/06 , H04M1/72525 , H04M1/72561 , H04M1/72563 , H04N21/41407 , H04N21/435 , H04N21/4782 , H04N21/4828 , H04N21/84 , H04N21/8543
摘要： A novel system, method and computer program product for accessing digital media files via a mobile phone device having a user interface adapted for initiating search requests for digital content associated with a searched category. The method for providing digital content for user search and selection via his/her mobile phone comprises receiving metadata content from one or more content providers equipped to transmit digital content to a user's digital phone, aggregating the received metadata content including heterogeneous content types, and generating a catalogue representing the aggregated metadata content. A further step includes accessing the aggregated metadata content catalogue and retrieving catalogued metadata in accordance with a received user request. A single web page including metadata from the aggregated metadata content catalogue is generated that is adapted for receipt by the mobile phone and presentation via the user interface, thereby providing a user with integrated access to multiple heterogeneous content types via the single web page. The aggregating of the received metadata content includes bundling of metadata content associated with the heterogeneous content types. In one aspect, the bundling of metadata content associated with the heterogeneous content types is theme-based.
摘要翻译：一种用于经由具有用于发起与搜索类别相关联的数字内容的搜索请求的用户界面的移动电话设备访问数字媒体文件的新型系统，方法和计算机程序产品。用于通过他/她的移动电话提供用于用户搜索和选择的数字内容的方法包括从一个或多个内容提供商接收元数据内容，所述内容提供商被配备为向用户的数字电话传输数字内容，聚合接收的包括异构内容类型的元数据内容，以及生成表示汇总的元数据内容的目录。另一步骤包括根据接收到的用户请求访问聚合的元数据内容目录并检索编目的元数据。生成包括来自聚合的元数据内容目录的元数据的单个网页，其适于由移动电话接收和经由用户界面呈现，从而通过单个网页向用户提供对多个异构内容类型的集成访问。接收的元数据内容的聚合包括与异构内容类型相关联的元数据内容的捆绑。在一个方面，与异构内容类型相关联的元数据内容的捆绑是基于主题的。

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