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1. 发明申请

US20060157823A1 HIGH PERFORMANCE INTEGRATED VERTICAL TRANSISTORS AND METHOD OF MAKING THE SAME 失效
标题翻译：高性能集成垂直晶体管及其制造方法
公开(公告)号：US20060157823A1
公开(公告)日：2006-07-20
申请号：US10905685
申请日：2005-01-17
申请人： David Sheridan , Peter Gray , Jeffrey Johnson , Qizhi Liu
发明人： David Sheridan , Peter Gray , Jeffrey Johnson , Qizhi Liu
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L21/82285 , H01L27/0826 , H01L29/0821 , H01L29/7378
摘要： A complementary bipolar transistor is fabricated using an available a portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.
摘要翻译：使用可用的硅锗（SiGe）低温外延层的一部分作为垂直NPN晶体管的升高的基极区域和与垂直PNP集电极层相同的SiGe LTE层的另一部分来制造互补双极晶体管。互补的晶体管对垂直对齐并在单个方向上工作。

2. 发明申请

US20070001264A1 High performance integrated vertical transistors and method of making the same 审中-公开
标题翻译：高性能集成垂直晶体管及其制作方法
公开(公告)号：US20070001264A1
公开(公告)日：2007-01-04
申请号：US11516007
申请日：2006-09-06
申请人： David Sheridan , Peter Gray , Jeffrey Johnson , Qizhi Liu
发明人： David Sheridan , Peter Gray , Jeffrey Johnson , Qizhi Liu
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L21/82285 , H01L27/0826 , H01L29/0821 , H01L29/7378
摘要： A complementary bipolar transistor is fabricated using an available a portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.
摘要翻译：使用可用的硅锗（SiGe）低温外延层的一部分作为垂直NPN晶体管的升高的基极区域和与垂直PNP集电极层相同的SiGe LTE层的另一部分来制造互补双极晶体管。互补的晶体管对垂直对齐并在单个方向上工作。

3. 发明申请

US20080067623A1 LATERAL SILICIDED DIODES 有权
标题翻译：横向硅胶二极管
公开(公告)号：US20080067623A1
公开(公告)日：2008-03-20
申请号：US11944839
申请日：2007-11-26
申请人： Douglas Coolbaugh , Jeffrey Johnson , Xuefeng Liu , Bradley Orner , Robert Rassel , David Sheridan
发明人： Douglas Coolbaugh , Jeffrey Johnson , Xuefeng Liu , Bradley Orner , Robert Rassel , David Sheridan
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L29/0657 , H01L29/417 , H01L29/66136 , H01L29/66143 , H01L29/861 , H01L29/868
摘要： A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.
摘要翻译：制造横向二极管的结构和方法。二极管包括肖特基二极管和PIN二极管。制造方法包括在硅衬底中形成一个或多个掺杂区域和更多沟槽，并在沟槽的侧壁上形成金属硅化物。横向二极管的制造可以与场效应，双极和SiGe双极晶体管的制造集成。

4. 发明申请

US20050245038A1 Novel varactors for CMOS and BiCMOS technologies 失效
标题翻译：用于CMOS和BiCMOS技术的新型变容二极管
公开(公告)号：US20050245038A1
公开(公告)日：2005-11-03
申请号：US11053721
申请日：2005-02-08
申请人： Douglas Coolbaugh , James Dunn , Michael Gordon , Mohamed Hammad , Jeffrey Johnson , David Sheridan
发明人： Douglas Coolbaugh , James Dunn , Michael Gordon , Mohamed Hammad , Jeffrey Johnson , David Sheridan
IPC分类号： H01L21/8222 , H01L27/08 , H01L29/93 , H01L29/94
CPC分类号： H01L27/0811 , H01L27/0808 , H01L29/93 , H01L29/94
摘要： Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.
摘要翻译：提供了具有高可调性和/或与之相关的高品质因素的变形反应器及其制造方法。公开的一种类型的变容二极管是准超突发的基极 - 集电极结变容二极管，其包括在子集电极区域顶部具有第一导电类型的集电极区域的基板，所述集电极区域中存在多个隔离区域; 位于至少一对隔离区之间的贯穿植入区; 所述SiGe层位于所述衬底的不包含直通注入区域的部分之上，所述SiGe层具有不同于所述第一导电类型的第二导电类型的非本征基区; 以及位于外部基极区域和子集电极区域之间的锑注入区域。所公开的另一种类型的变容二极管是MOS变容二极管，其至少包括多晶硅栅极区域和阱区域，其中多晶硅栅极区域和阱区域具有相反的极性。

5. 发明申请

US20050161770A1 Structure and method of hyper-abrupt junction varactors 有权
标题翻译：超突变结可变电抗器的结构和方法
公开(公告)号：US20050161770A1
公开(公告)日：2005-07-28
申请号：US11004877
申请日：2004-12-07
申请人： Douglas Coolbaugh , Stephen Furkay , Jeffrey Johnson , Robert Rassel , David Sheridan
发明人： Douglas Coolbaugh , Stephen Furkay , Jeffrey Johnson , Robert Rassel , David Sheridan
IPC分类号： H01L29/93 , H01L29/94 , H01L27/108
CPC分类号： H01L29/93 , H01L29/94
摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.
摘要翻译：提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

6. 发明申请

US20050161769A1 STRUCTURE AND METHOD FOR HYPER-ABRUPT JUNCTION VARACTORS 有权
标题翻译：超高压连接变压器的结构与方法
公开(公告)号：US20050161769A1
公开(公告)日：2005-07-28
申请号：US10707905
申请日：2004-01-23
申请人： Douglas Coolbaugh , Stephen Furkay , Jeffrey Johnson , Robert Rassel , David Sheridan
发明人： Douglas Coolbaugh , Stephen Furkay , Jeffrey Johnson , Robert Rassel , David Sheridan
IPC分类号： H01L29/93 , H01L29/94
CPC分类号： H01L29/93 , H01L29/94
摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.
摘要翻译：提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

7. 发明申请

US20210369124A1 MEASURING CAPILLARY REFILL TIME 有权
公开(公告)号：US20210369124A1
公开(公告)日：2021-12-02
申请号：US16887846
申请日：2020-05-29
申请人： David Sheridan , Matthew Lee Hansen , Andrew Kibler , Steven D. Baker , Richard Allen Sunderland , Richard H. Weitzel
发明人： David Sheridan , Matthew Lee Hansen , Andrew Kibler , Steven D. Baker , Richard Allen Sunderland , Richard H. Weitzel
IPC分类号： A61B5/02 , A61B5/00
摘要： A system for measuring capillary refill time includes a wearable device and a control unit. The wearable device includes a force sensor to obtain a force signal and an optical sensor to obtain an optical signal. The system ensures that an applied force is acceptable in both magnitude and duration, and that a duration over which the applied force is released or removed is acceptable. These factors can establish that a capillary refill time determined or calculated therein is accurate. The system can also determine the capillary refill time based on the force and optical signals obtained by the force and optical sensors, respectively.

8. 发明申请

US20180076310A1 ASYMMETRICAL BLOCKING BIDIRECTIONAL GALLIUM NITRIDE SWITCH 审中-公开
公开(公告)号：US20180076310A1
公开(公告)日：2018-03-15
申请号：US15244819
申请日：2016-08-23
申请人： David Sheridan
发明人： David Sheridan
IPC分类号： H01L29/778 , H01L29/40 , H01L29/20 , H01L29/205 , H01L29/423 , H01L29/49
CPC分类号： H01L29/7787 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/404 , H01L29/42356 , H01L29/4236 , H01L29/4966 , H01L29/66462 , H01L29/7786
摘要： A high electron mobility transistor (HEMT)gallium nitride (GaN) bidirectional blocking device includes a hetero-j unction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2 DEG) layer. The HEMT GaN bidirectional blocking device further includes a first source/drain electrode and a second source/drain electrode disposed on two opposite sides of a gate electrode disposed on top of said hetero-junction structure for controlling a current flow between the first and second source/drain electrodes in the 2 DEG layer wherein the gate electrode is disposed at a first distance from the first source/drain electrode and a second distance from the second source/drain electrode and the first distance is different from the second distance.

9. 发明授权

US09021409B2 Integration of data mining and static analysis for hardware design verification 有权
标题翻译：数据挖掘和静态分析的集成用于硬件设计验证
公开(公告)号：US09021409B2
公开(公告)日：2015-04-28
申请号：US13433909
申请日：2012-03-29
申请人： Shobha Vasudevan , David Sheridan , Lingyi Liu
发明人： Shobha Vasudevan , David Sheridan , Lingyi Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022
摘要： A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of the design.
摘要翻译：生成用于验证在寄存器传送级（RTL）表示的硬件设计的断言的方法包括通过设计运行模拟迹线以产生仿真数据; 提取关于感兴趣的变量的设计的领域特定信息; 使用模拟数据和域特定信息执行数据挖掘算法，通过机器学习针对域特定信息生成一组感兴趣的变量的候选断言，候选断言可能是不变的; 通过输出通过验证的候选断言作为不变量，对每个候选断言进行设计的形式验证; 迭代地将由每个故障候选者断言产生的反例跟踪反馈给算法，每个反例行轨迹包括设计中至少有一个附加变量，以前没有输入到数据挖掘算法中，从而增加设计状态空间的覆盖。

10. 发明申请

US20060172543A1 Graded junction termination extensions for electronic devices 失效
公开(公告)号：US20060172543A1
公开(公告)日：2006-08-03
申请号：US11201066
申请日：2005-08-09
申请人： J. Merrett , Tamara Isaacs-Smith , David Sheridan , John Williams
发明人： J. Merrett , Tamara Isaacs-Smith , David Sheridan , John Williams
IPC分类号： H01L21/302
CPC分类号： H01L29/0615 , H01L21/0465 , H01L29/1608 , Y10S438/931
摘要： A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

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