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1. 发明申请

US20130019216A1 INTEGRATION OF DATA MINING AND STATIC ANALYSIS FOR HARDWARE DESIGN VERIFICATION 有权
标题翻译：数据采集与硬件设计验证的静态分析综合
公开(公告)号：US20130019216A1
公开(公告)日：2013-01-17
申请号：US13433909
申请日：2012-03-29
申请人： Shobha Vasudevan , David Sheridan , Lingyi Liu , Hyung Sul Kim
发明人： Shobha Vasudevan , David Sheridan , Lingyi Liu , Hyung Sul Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022
摘要： A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of the design.
摘要翻译：生成用于验证在寄存器传送级（RTL）表示的硬件设计的断言的方法包括通过设计运行模拟迹线以产生仿真数据; 提取关于感兴趣的变量的设计的领域特定信息; 使用模拟数据和域特定信息执行数据挖掘算法，通过机器学习针对域特定信息生成一组感兴趣的变量的候选断言，候选断言可能是不变的; 通过输出通过验证的候选断言作为不变量，对每个候选断言进行设计的形式验证; 迭代地将由每个故障候选者断言产生的反例跟踪反馈给算法，每个反例行轨迹包括设计中至少有一个附加变量，以前没有输入到数据挖掘算法中，从而增加设计状态空间的覆盖。

2. 发明授权

US09021409B2 Integration of data mining and static analysis for hardware design verification 有权
标题翻译：数据挖掘和静态分析的集成用于硬件设计验证
公开(公告)号：US09021409B2
公开(公告)日：2015-04-28
申请号：US13433909
申请日：2012-03-29
申请人： Shobha Vasudevan , David Sheridan , Lingyi Liu
发明人： Shobha Vasudevan , David Sheridan , Lingyi Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022
摘要： A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of the design.
摘要翻译：生成用于验证在寄存器传送级（RTL）表示的硬件设计的断言的方法包括通过设计运行模拟迹线以产生仿真数据; 提取关于感兴趣的变量的设计的领域特定信息; 使用模拟数据和域特定信息执行数据挖掘算法，通过机器学习针对域特定信息生成一组感兴趣的变量的候选断言，候选断言可能是不变的; 通过输出通过验证的候选断言作为不变量，对每个候选断言进行设计的形式验证; 迭代地将由每个故障候选者断言产生的反例跟踪反馈给算法，每个反例行轨迹包括设计中至少有一个附加变量，以前没有输入到数据挖掘算法中，从而增加设计状态空间的覆盖。

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