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1. 发明申请

US20080067623A1 LATERAL SILICIDED DIODES 有权
标题翻译：横向硅胶二极管
公开(公告)号：US20080067623A1
公开(公告)日：2008-03-20
申请号：US11944839
申请日：2007-11-26
申请人： Douglas Coolbaugh , Jeffrey Johnson , Xuefeng Liu , Bradley Orner , Robert Rassel , David Sheridan
发明人： Douglas Coolbaugh , Jeffrey Johnson , Xuefeng Liu , Bradley Orner , Robert Rassel , David Sheridan
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L29/0657 , H01L29/417 , H01L29/66136 , H01L29/66143 , H01L29/861 , H01L29/868
摘要： A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.
摘要翻译：制造横向二极管的结构和方法。二极管包括肖特基二极管和PIN二极管。制造方法包括在硅衬底中形成一个或多个掺杂区域和更多沟槽，并在沟槽的侧壁上形成金属硅化物。横向二极管的制造可以与场效应，双极和SiGe双极晶体管的制造集成。

2. 发明申请

US20070105354A1 BURIED SUBCOLLECTOR FOR HIGH FREQUENCY PASSIVE DEVICES 失效
标题翻译：用于高频无源器件的BURIED SUBCOLLECTOR
公开(公告)号：US20070105354A1
公开(公告)日：2007-05-10
申请号：US11164108
申请日：2005-11-10
申请人： Douglas Coolbaugh , Xuefeng Liu , Robert Rassel , David Sheridan
发明人： Douglas Coolbaugh , Xuefeng Liu , Robert Rassel , David Sheridan
IPC分类号： H01L21/425
CPC分类号： H01L21/8249 , H01L29/0821 , H01L29/66272
摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.
摘要翻译：一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比）。本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。

3. 发明申请

US20070096257A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20070096257A1
公开(公告)日：2007-05-03
申请号：US11163882
申请日：2005-11-02
申请人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
发明人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
IPC分类号： H01L27/102
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

4. 发明申请

US20080099787A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080099787A1
公开(公告)日：2008-05-01
申请号：US11873696
申请日：2007-10-17
申请人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
发明人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
IPC分类号： H01L27/06
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

5. 发明申请

US20070241421A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 失效
标题翻译：半导体结构及其制造方法
公开(公告)号：US20070241421A1
公开(公告)日：2007-10-18
申请号：US11279934
申请日：2006-04-17
申请人： Xuefeng Liu , Robert Rassel , Steven Voldman
发明人： Xuefeng Liu , Robert Rassel , Steven Voldman
IPC分类号： H01L21/331 , H01L29/00
CPC分类号： H01L29/7322 , H01L27/0921 , H01L29/0821 , H01L29/66272
摘要： A structure comprises a deep subcollector buried in a first region of a dual epitaxial layer and a reachthrough structure in contact with the deep subcollector to provide a low-resistive shunt which prevents CMOS latch-up for a first device. The structure may additionally include a near subcollector formed in a higher region than the deep subcollector and under another device. At least one reachthrough electrically connects the deep subcollector and the near subcollector. The method includes forming a merged triple well double epitaxy/double subcollector.
摘要翻译：一种结构包括埋藏在双外延层的第一区域中的深子集电极和与深子集电极接触的到达结构，以提供阻止第一器件的CMOS闩锁的低电阻分流。该结构可以另外包括形成在比深层子集电极更高的区域内并且在另一器件下形成的近子集电极。至少一个通孔电连接深子集电极和近子集电极。该方法包括形成合并三阱双外延/双子集电极。

6. 发明授权

US09448162B2 Time-resolved single-photon or ultra-weak light multi-dimensional imaging spectrum system and method 有权
标题翻译：时间分辨单光子或超弱光多维成像光谱系统及方法
公开(公告)号：US09448162B2
公开(公告)日：2016-09-20
申请号：US14351028
申请日：2012-05-14
申请人： Guangjie Zhai , Wenkai Yu , Xuefeng Liu , Xuri Yao , Chao Wang , Zhibin Sun
发明人： Guangjie Zhai , Wenkai Yu , Xuefeng Liu , Xuri Yao , Chao Wang , Zhibin Sun
IPC分类号： G01N21/25 , G01N21/64 , G01N21/17 , H03K21/38 , G01J1/04 , G01J1/42 , G01S17/89 , G01S7/481 , G01S7/486 , G02B26/08
CPC分类号： G01N21/255 , G01J1/0414 , G01J1/4228 , G01N21/17 , G01N21/6456 , G01S7/4816 , G01S7/486 , G01S17/89 , G02B26/0833 , H03K21/38
摘要： A single-photon or ultra-weak light multi-D imaging spectral system and method. In order to realize rough time resolution, a time-resolved single-photon counting 2D imaging system for forming color or grey imaging is provided. Moreover, in order to realize high-precision time resolution, the system comprises a light source, an imaging spectral measurement unit, an electric detection unit, a system control unit and an algorithm unit. The light carrying information of an object is imaged on a spatial light modulator and randomly modulated according to compressed sensing theory, emergent light of a grating is collected using a point or array single-photon detector, the number of photons and photon arrival time are recorded, and reconstruction is carried out using the compressed sensing algorithm and related algorithm of the spectral imaging. The system provides single-photon detection sensitivity, high time resolution and wide spectral range, and can be applied in numerous new high-tech industries.
摘要翻译：单光子或超弱光多D成像光谱系统及方法。为了实现粗糙的时间分辨率，提供了用于形成彩色或灰度成像的时间分辨的单光子计数2D成像系统。此外，为了实现高精度时间分辨率，该系统包括光源，成像光谱测量单元，电检测单元，系统控制单元和算法单元。物体的光携带信息在空间光调制器上成像，并且根据压缩感测理论随机调制，使用点或阵列单光子检测器收集光栅的出射光，记录光子数和光子到达时间，并利用压缩感知算法和相关的光谱成像算法进行重建。该系统提供单光子检测灵敏度高，时间分辨率高，光谱范围广，可应用于众多新兴高科技行业。

7. 发明授权

US09080990B2 Illumination subsystems of a metrology system, metrology systems, and methods for illuminating a specimen for metrology measurements 有权
标题翻译：计量系统的照明子系统，计量系统以及用于计量测量的照明样本的方法
公开(公告)号：US09080990B2
公开(公告)日：2015-07-14
申请号：US13061936
申请日：2009-09-29
申请人： Yung-Ho (Alex) Chuang , Vladimir Levinski , Xuefeng Liu
发明人： Yung-Ho (Alex) Chuang , Vladimir Levinski , Xuefeng Liu
IPC分类号： G01N21/55 , G01N21/95 , G01N21/47
CPC分类号： G01N21/9501 , G01N2021/479
摘要： Illumination subsystems of a metrology system, metrology systems, and methods for illuminating a specimen for metrology measurements are provided. One illumination subsystem includes a light source configured to generate coherent pulses of light and a dispersive element positioned in the path of the coherent pulses of light, which is configured to reduce coherence of the pulses of light by mixing spatial and temporal characteristics of light distribution in the pulses of light. The illumination subsystem also includes an electro-optic modulator positioned in the path of the pulses of light exiting the dispersive element and which is configured to reduce the coherence of the pulses of light by temporally modulating the light distribution in the pulses of light. The illumination subsystem is configured to direct the pulses of light from the electro-optic modulator to a specimen positioned in the metrology system.
摘要翻译：提供了计量系统的照明子系统，计量系统和用于度量测量的照明样本的方法。一个照明子系统包括被配置为产生相干的光脉冲的光源和位于相干脉冲光的路径中的色散元件，该色散元件被配置为通过将光分布的空间和时间特征混合在一起来减小光脉冲的相干性光的脉冲。照明子系统还包括位于离开色散元件的光的脉冲的路径中的电光调制器，其被配置为通过暂时调制光脉冲中的光分布来减小光脉冲的相干性。照明子系统被配置为将来自电光调制器的光的脉冲引导到位于计量系统中的样本。

8. 发明授权

US09059138B2 Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure 有权
标题翻译：具有减小的集电极长度的异质结双极晶体管，制造方法和设计结构
公开(公告)号：US09059138B2
公开(公告)日：2015-06-16
申请号：US13358180
申请日：2012-01-25
申请人： Renata Camillo-Castillo , Zhong-Xiang He , Jeffrey B. Johnson , Qizhi Liu , Xuefeng Liu
发明人： Renata Camillo-Castillo , Zhong-Xiang He , Jeffrey B. Johnson , Qizhi Liu , Xuefeng Liu
IPC分类号： H01L29/737 , G06F17/50 , H01L21/331 , H01L29/417 , H01L29/66 , H01L29/10
CPC分类号： H01L29/417 , H01L29/1004 , H01L29/66242 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.
摘要翻译：提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。收集器触点有利地延伸穿过外部基极层的至少一部分。

9. 发明授权

US08946013B2 Lateral diffusion field effect transistor with drain region self-aligned to gate electrode 有权
标题翻译：侧向扩散场效应晶体管，漏极区自对准至栅电极
公开(公告)号：US08946013B2
公开(公告)日：2015-02-03
申请号：US13364663
申请日：2012-02-02
申请人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
发明人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L21/00 , H01L21/265 , H01L29/66 , H01L29/78 , H01L29/10
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/1045 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.
摘要翻译：形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。因此，漏极区域与栅电极的边缘自对准。一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。在形成漏极区域之后，一次性结构被去除。漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

10. 发明授权

US08860191B2 On-chip transmission line structures with balanced phase delay 有权
标题翻译：具有平衡相位延迟的片上传输线结构
公开(公告)号：US08860191B2
公开(公告)日：2014-10-14
申请号：US13168512
申请日：2011-06-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L23/66 , H01P1/18 , H01L23/522
CPC分类号： H01L23/5222 , H01L23/5225 , H01L23/66 , H01L2223/6638 , H01L2924/0002 , H01P1/184 , Y10T29/49117 , H01L2924/00
摘要： A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.
摘要翻译：一种传输线路结构，相关设计结构及其相关方法。公开了一种结构，其具有：形成在半导体衬底上的多个布线层; 位于布线层中的一对相邻的第一和第二信号线，其中第一信号线包括形成在第一布线层上的第一部分和形成在第二布线层上的第二部分; 第一介电结构，其具有位于第一部分和接地屏蔽之间的第一介电常数; 以及具有不同于所述第一介电常数的第二介电常数的次级介电结构，所述第二介电结构位于所述第二部分和所述接地屏蔽之间，并且所述第二电介质层与所述第二部分共面延伸并且具有长度为基本上与第二部分相同。

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