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    • 9. 发明申请
    • MEMORY MAPPED INPUT/OUTPUT BUS ADDRESS RANGE TRANSLATION
    • 存储映射输入/输出总线地址范围翻译
    • US20110276779A1
    • 2011-11-10
    • US12774210
    • 2010-05-05
    • David R. EngebretsenSteven M. ThurberCurtis C. Wollbrink
    • David R. EngebretsenSteven M. ThurberCurtis C. Wollbrink
    • G06F12/10G06F13/00
    • G06F13/404G06F13/4022
    • In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.
    • 在一个实施例中,北芯片接收辅助总线标识符,其识别紧邻南芯片桥上下游的总线,标识可到达桥下游的所有总线的最高总线标识符的下级总线标识符,以及 MMIO总线地址范围包括内存基础和内存限制。 北芯片将桥标识符和南芯片标识符的翻译写入辅助总线标识符,从属总线标识符和MMIO总线地址范围。 北芯片将辅助总线标识符,下级总线标识符,存储器基准和存储器限制发送到桥。 桥接器存储桥中的辅助总线标识符,下级总线标识符,存储器基准和存储器限制。