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1. 发明授权

US08327055B2 Translating a requester identifier to a chip identifier 失效
标题翻译：将请求者标识符转换为芯片标识符
公开(公告)号：US08327055B2
公开(公告)日：2012-12-04
申请号：US12758383
申请日：2010-04-12
申请人： William J. Armstrong , David R. Engebretsen , Steven M. Thurber , Curtis C. Wollbrink , Adalberto G. Yanes
发明人： William J. Armstrong , David R. Engebretsen , Steven M. Thurber , Curtis C. Wollbrink , Adalberto G. Yanes
IPC分类号： G06F13/14
CPC分类号： G06F13/4027
摘要： In an embodiment a translation of RID (requester identifier) ranges to identifiers of north chips is stored into a south chip. A command that comprises a command RID is received at the south chip from a device. In response, a RID range is determined that encompasses the command RID, and a north chip identifier is found that is assigned a virtual function identified by the command RID. The command is sent from the south chip to the north chip identified by the north chip identifier. The translation comprises a RID compare value and a RID mask. A determination is made that the RID range encompasses the command RID by performing a logical-and operation on the command RID and the RID mask and comparing a result of the logical-and operation to the RID compare value.
摘要翻译：在一个实施例中，将RID（请求者标识符）范围转换为北芯片的标识符被存储在南芯片中。包括命令RID的命令在设备的南芯片处被接收。作为响应，确定包含命令RID的RID范围，并且找到被分配了由命令RID识别的虚拟功能的北芯片标识符。该命令从南芯片发送到由北芯片标识符标识的北芯片。翻译包括RID比较值和RID掩码。通过对命令RID和RID掩码执行逻辑和操作来确定RID范围包含命令RID，并将逻辑和操作的结果与RID比较值进行比较。

2. 发明申请

US20110252174A1 HIERARCHICAL TO PHYSICAL MEMORY MAPPED INPUT/OUTPUT TRANSLATION 失效
标题翻译：物理内存映射输入/输出翻译
公开(公告)号：US20110252174A1
公开(公告)日：2011-10-13
申请号：US12758256
申请日：2010-04-12
申请人： William J. Armstrong , Scott N. Dunham , David R. Engebretsen , Gregory M. Nordstrom , Steven M. Thurber , Curtis C. Wollbrink , Adalberto G. Yanes
发明人： William J. Armstrong , Scott N. Dunham , David R. Engebretsen , Gregory M. Nordstrom , Steven M. Thurber , Curtis C. Wollbrink , Adalberto G. Yanes
IPC分类号： G06F13/36 , G06F12/00
CPC分类号： G06F12/0292 , G06F2212/206
摘要： In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO address that is within the hierarchical MMIO address range is replaced in the transaction with the identifier of the bridge and with a physical MMIO address that is within the physical MMIO address range in the south chip. The transaction is sent to the device that is connected to the bridge in the south chip. The physical MMIO address range specifies a range of physical MMIO addresses in memory in the device.
摘要翻译：在一个实施例中，分层MMIO地址范围到物理MMIO地址范围的转换和南芯片中的桥的标识符被写入到北芯片。收到包含分层MMIO地址的事务。处于分层MMIO地址范围内的分层MMIO地址在事务中被替换为桥接器的标识符，以及在南芯片的物理MMIO地址范围内的物理MMIO地址。事务发送到连接到南芯片桥的设备。物理MMIO地址范围指定设备内存中物理MMIO地址的范围。

3. 发明申请

US20110252173A1 TRANSLATING A REQUESTER IDENTIFIER TO A CHIP IDENTIFIER 失效
标题翻译：将请求者标识符转换为芯片标识符
公开(公告)号：US20110252173A1
公开(公告)日：2011-10-13
申请号：US12758383
申请日：2010-04-12
申请人： William J. Armstrong , David R. Engebretsen , Steven M. Thurber , Curtis C. Wollbrink , Adalberto G. Yanes
发明人： William J. Armstrong , David R. Engebretsen , Steven M. Thurber , Curtis C. Wollbrink , Adalberto G. Yanes
IPC分类号： G06F13/14
CPC分类号： G06F13/4027
摘要： In an embodiment a translation of RID (requester identifier) ranges to identifiers of north chips is stored into a south chip. A command that comprises a command RID is received at the south chip from a device. In response, a RID range is determined that encompasses the command RID, and a north chip identifier is found that is assigned a virtual function identified by the command RID. The command is sent from the south chip to the north chip identified by the north chip identifier. The translation comprises a RID compare value and a RID mask. A determination is made that the RID range encompasses the command RID by performing a logical-and operation on the command RID and the RID mask and comparing a result of the logical-and operation to the RID compare value.
摘要翻译：在一个实施例中，将RID（请求者标识符）范围转换为北芯片的标识符被存储在南芯片中。包括命令RID的命令在设备的南芯片处被接收。作为响应，确定包含命令RID的RID范围，并且找到被分配了由命令RID识别的虚拟功能的北芯片标识符。该命令从南芯片发送到由北芯片标识符标识的北芯片。翻译包括RID比较值和RID掩码。通过对命令RID和RID掩码执行逻辑和操作来确定RID范围包含命令RID，并将逻辑和操作的结果与RID比较值进行比较。

4. 发明申请

US20080052441A1 Dynamically Scalable Queues for Performance Driven PCI Express Memory Traffic 失效
标题翻译：用于性能驱动的PCI Express内存流量的动态可扩展队列
公开(公告)号：US20080052441A1
公开(公告)日：2008-02-28
申请号：US11466142
申请日：2006-08-22
申请人： Ronald E. Freking , Philip R. Hillier , Curtis C. Wollbrink
发明人： Ronald E. Freking , Philip R. Hillier , Curtis C. Wollbrink
IPC分类号： G06F13/36
CPC分类号： G06F13/385
摘要： A method, computer system, and PCI Express device/protocol for enabling high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) utility is provided within the enhanced PCI Express protocol to monitor ongoing, current data transfer and manage when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding.
摘要翻译：一种方法，计算机系统和PCI Express设备/协议，用于实现多种不同IO配置的高性能IO数据传输，其包括IO链路上的可变分组大小和/或可变/不同数量的事务。增强了PCI Express协议，以支持计数器的使用和动态可变队列大小。除了标准队列条目之外，提供/保留了几个（或选定数量的）动态可变队列条目，并且在增强型PCI Express协议内提供动态队列修改（DQM）实用程序，以监视正在进行的当前数据传输和管理当基于在PCI Express IO链路上传输的当前数据流量来修改（增加或减少）队列条目的大小时。增强的PCI Express协议提供了许多大数据分组有效传输的平衡点，同时限制了每个未知大小的数据包的数量。

5. 发明授权

US09043526B2 Versatile lane configuration using a PCIe PIe-8 interface 有权
标题翻译：使用PCIe PIe-8接口的通用通道配置
公开(公告)号：US09043526B2
公开(公告)日：2015-05-26
申请号：US13528146
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： G06F13/40
CPC分类号： G06F13/4018 , G06F9/4411 , G06F13/423
摘要： Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.
摘要翻译：每个PCIe设备可以包括支持多个不同通道配置的媒体访问控制（MAC）接口和物理（PHY）接口。这些接口可以包括支持1×32,2×16,4×8,8×4,16×2和32×1通信的硬件模块。代替使用专用迹线将MAC接口中的每个硬件模块物理连接到PHY接口中的相应硬件模块，该设备可以包括两个总线控制器，其仲裁哪些硬件模块连接到耦合两个接口的内部总线。当需要不同的通道配置时，总线控制器将相应的硬件模块耦合到内部总线。以这种方式，不同的通道配置与其他通道配置共享总线的相同通道（和线）。因此，共享总线仅需要包括足够的通道（和电线），以适应最宽的通道配置。

6. 发明申请

US20130346665A1 VERSATILE LANE CONFIGURATION USING A PCIE PIE-8 INTERFACE 有权
公开(公告)号：US20130346665A1
公开(公告)日：2013-12-26
申请号：US13528146
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： G06F13/20
CPC分类号： G06F13/4018 , G06F9/4411 , G06F13/423
摘要： Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.

7. 发明申请

US20090125666A1 DYNAMICALLY SCALABLE QUEUES FOR PERFORMANCE DRIVEN PCI EXPRESS MEMORY TRAFFIC 审中-公开
标题翻译：性能强大的PCI Express Express存储器交换机动态可扩展性
公开(公告)号：US20090125666A1
公开(公告)日：2009-05-14
申请号：US12357098
申请日：2009-01-21
申请人： Ronald E. Freking , Philip R. Hillier, III , Curtis C. Wollbrink
发明人： Ronald E. Freking , Philip R. Hillier, III , Curtis C. Wollbrink
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： A computer program product for implementing a method within a data processing system and a PCI Express protocol for enabling high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) utility is provided within the enhanced PCI Express protocol to monitor ongoing, current data transfer and manage when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding.
摘要翻译：一种用于实现数据处理系统和PCI Express协议中的方法的计算机程序产品，用于实现用于多个不同IO配置的高性能IO数据传输，其包括IO链路上的可变分组大小和/或可变/不同数量的事务。增强了PCI Express协议，以支持计数器的使用和动态可变队列大小。除了标准队列条目之外，提供/保留了几个（或选定数量的）动态可变队列条目，并且在增强型PCI Express协议内提供动态队列修改（DQM）实用程序，以监视正在进行的当前数据传输和管理当基于在PCI Express IO链路上传输的当前数据流量来修改（增加或减少）队列条目的大小时。增强的PCI Express协议提供了许多大数据分组有效传输的平衡点，同时限制了每个未知大小的数据包的数量。

8. 发明授权

US08949499B2 Using a PCI standard hot plug controller to modify the hierarchy of a distributed switch 有权
公开(公告)号：US08949499B2
公开(公告)日：2015-02-03
申请号：US13528192
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： H05K7/10 , G06F13/40 , G06F13/20
CPC分类号： G06F13/4081 , G06F13/20
摘要： The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.

9. 发明授权

US08706938B2 Bandwidth limiting on generated PCIE packets from debug source 失效
标题翻译：从调试源生成的PCIE数据包的带宽限制
公开(公告)号：US08706938B2
公开(公告)日：2014-04-22
申请号：US13528224
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： G06F13/36 , G06F13/362
CPC分类号： G06F11/263 , G06F13/00 , G06F13/1605 , G06F13/36 , G06F2213/0026
摘要： Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.
摘要翻译：用于执行用于调节带宽的操作的方法，电路和系统，所述操作包括在存储器处接收调试数据分组和用于在共享总线上传送的功能数据分组。然后，该操作通过共享总线将功能数据分组和一个或多个调试数据分组根据调制数据分组的预定比率发送到功能数据分组。然后，该操作将接收到的调试数据分组中的一个或多个丢弃在存储器处，并维持一个或多个丢弃的调试数据分组的计数。然后，操作基于计数更新预定义的比例，并且使用更新的预定义比率来发送功能数据分组和一个或多个调试数据分组。

10. 发明申请

US20130346801A1 BANDWIDTH LIMITING ON GENERATED PCIE PACKETS FROM DEBUG SOURCE 失效
标题翻译：来自调试源的生成PCIE分组的带宽限制
公开(公告)号：US20130346801A1
公开(公告)日：2013-12-26
申请号：US13528224
申请日：2012-06-20
申请人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
发明人： Ronald E. Freking , Elizabeth A. McGlone , Daniel R. Spach , Curtis C. Wollbrink
IPC分类号： G06F11/28
CPC分类号： G06F11/263 , G06F13/00 , G06F13/1605 , G06F13/36 , G06F2213/0026
摘要： Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.
摘要翻译：用于执行用于调节带宽的操作的方法，电路和系统，所述操作包括在存储器处接收调试数据分组和用于在共享总线上传送的功能数据分组。然后，该操作通过共享总线将功能数据分组和一个或多个调试数据分组根据调制数据分组的预定比率发送到功能数据分组。然后，该操作将接收到的调试数据分组中的一个或多个丢弃在存储器处，并维持一个或多个丢弃的调试数据分组的计数。然后，操作基于计数更新预定义的比例，并且使用更新的预定义比率来发送功能数据分组和一个或多个调试数据分组。

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