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1. 发明授权

US06532553B1 Debugging data processing systems 有权
标题翻译：调试数据处理系统
公开(公告)号：US06532553B1
公开(公告)日：2003-03-11
申请号：US09407846
申请日：1999-09-29
申请人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
发明人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
IPC分类号： H02H305
CPC分类号： G06F11/3636 , G06F9/30003 , G06F9/3005
摘要： A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.
摘要翻译：提供了具有主处理器4和协处理器26的数据处理系统。当处于调试模式时，向主处理器4和协处理器26提供不同的指令。协处理器26被提供有协处理器调试数据生成指令（MCR），而主处理器4被提供有主处理器数据捕获指令（LDR）。协处理器26通过控制表示数据处理装置2的状态的调试数据来响应MCR指令，数据处理装置2将被放置在数据总线24上，从LDR指令的控制下由主处理器4读取数据总线24。

2. 发明授权

US07213095B2 Bus transaction management within data processing systems 有权
标题翻译：数据处理系统内的总线事务管理
公开(公告)号：US07213095B2
公开(公告)日：2007-05-01
申请号：US10862884
申请日：2004-06-08
申请人： Peter Guy Middleton , David John Gwilt , Ian Victor Devereux , Bruce James Mathewson , Antony John Harris , Richard Roy Grisenthwaite
发明人： Peter Guy Middleton , David John Gwilt , Ian Victor Devereux , Bruce James Mathewson , Antony John Harris , Richard Roy Grisenthwaite
IPC分类号： G06F13/36
CPC分类号： G06F13/1631
摘要： A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.
摘要翻译：数据处理系统具有总线，该总线具有分开的写通道W和读通道R，通过该通道进行总线交易。总线事务缓冲器34设置在总线结构内以缓冲写入请求，特别是为了减轻与相对较慢的总线从站相关联的问题。总线事务缓冲器34响应于与写入请求相关联的存储器地址和通过它们的读取请求，以将它们识别到相同存储器地址或者在预定范围内的存储器地址，以便确保那些交易，读取以遵循写入，或者在写入缓冲写入数据值之后满足读取，然后刷新读取请求，使其不到达其最终目的地。

3. 发明授权

US06721861B2 Indicator of validity status information for data storage within a data processing system 有权
标题翻译：数据处理系统内数据存储的有效状态信息指示符
公开(公告)号：US06721861B2
公开(公告)日：2004-04-13
申请号：US10330478
申请日：2002-12-30
申请人： Peter Guy Middleton , David Michael Bull
发明人： Peter Guy Middleton , David Michael Bull
IPC分类号： G06F1200
CPC分类号： G06F12/0891 , G06F12/00
摘要： A valid memory 2 is provided storing valid words 8 with bit positions indicating whether corresponding cache lines within a cache memory 7 store valid data. Flip-flop circuits 4 are provided to indicate whether or not the valid words 8 within the valid memory 2 are themselves valid. The number of valid words 8 corresponding to an individual flip-flop circuit 4 varies in dependence upon the size of the valid memory 2. Thus, for example, a single flip-flop circuit 4 may indicate whether one, two, four or eight valid words 8 from the valid memory 2 are storing valid data depending upon the particular size of the valid memory 2 employed.
摘要翻译：提供有效存储器2，存储有效字8，其中位位置指示高速缓冲存储器7内相应的高速缓存线是否存储有效数据。提供触发器电路4以指示有效存储器2内的有效字8本身是否有效。对应于单个触发器电路4的有效字8的数量根据有效存储器2的大小而变化。因此，例如，单个触发器电路4可以指示是否有一个，两个，四个或八个有效来自有效存储器2的字8根据所采用的有效存储器2的特定尺寸来存储有效数据。

4. 发明授权

US06353879B1 Memory address translation in a data processing system 有权
标题翻译：数据处理系统中的内存地址转换
公开(公告)号：US06353879B1
公开(公告)日：2002-03-05
申请号：US09252927
申请日：1999-02-19
申请人： Peter Guy Middleton , David Michael Bull
发明人： Peter Guy Middleton , David Michael Bull
IPC分类号： G06F1200
CPC分类号： G06F12/10 , G06F12/1054 , G06F2212/654
摘要： A data processing system 2 is provided with a processor core 4 that issues virtual addresses VA that are translated to mapped addresses MA by an address translation circuit 6 based upon a predicted address mapping. The mapped address MA is used for a memory access within a memory system 8. The mapped address MA starts to be used before a mapping validity circuit 6 has determined whether or not the predicted translation was valid. Accordingly, if the predicted address translation turns out to be invalid, then the memory access is aborted. The state of the processor core is preserved either by stretching the processor clock signal or by continuing the processor clock signal and waiting the processor 4. The memory system 8 then restarts the memory access with the correct translated address.
摘要翻译：数据处理系统2具有处理器核心4，处理器核心4基于预测的地址映射，通过地址转换电路6发布被映射到映射地址MA的虚拟地址VA。映射地址MA用于存储器系统8内的存储器访问。映射地址MA开始在映射有效性电路6确定预测翻译是否有效之前被使用。因此，如果预测的地址转换是无效的，则存储器访问被中止。通过拉伸处理器时钟信号或继续处理器时钟信号并等待处理器4来保留处理器核心的状态。然后，存储器系统8以正确翻译的地址重新启动存储器访问。

5. 发明授权

US06826670B2 Accessing memory units in a data processing apparatus 有权
标题翻译：访问数据处理设备中的存储器单元
公开(公告)号：US06826670B2
公开(公告)日：2004-11-30
申请号：US10158105
申请日：2002-05-31
申请人： Peter Guy Middleton , David Michael Bull , Gary Campbell
发明人： Peter Guy Middleton , David Michael Bull , Gary Campbell
IPC分类号： G06F1200
CPC分类号： G06F12/0888 , G06F12/0215 , Y02D10/13
摘要： The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access. Instead, prediction logic is arranged to predict the one or more predetermined attributes, and clock generation logic is responsive to the predictive predetermined attributes from the prediction logic to select which one of the memory units is to be clocked during performance of the access, and to issue a clock signal to that memory unit. Checking logic is then provided to determine whether the predetermined attributes generated by the attribute generation logic agree with the predicted predetermined attributes, and if not, to reinitiate the access, in which event the clock generation logic is arranged to reselect one of the memory units using the predetermined attributes as determined by the attribute generation logic. This approach enables high speed processing of access requests, whilst achieving significant power savings over prior art systems where multiple memory units are clocked speculatively in parallel.
摘要翻译：本发明涉及用于访问数据处理装置中的存储单元的技术。数据处理装置包括用于存储数据值的多个存储器单元，用于发出指定对数据值对存储器单元进行访问的访问请求的处理器核心，以及用于执行由数据值指定的访问的存储器控制器访问请求。提供属性生成逻辑用于从访问请求确定一个或多个预定属性，以便在执行访问时验证哪个存储单元应被使用。然而，存储器控制器不等待直到在开始访问之前由属性生成逻辑执行这样的确定。相反，预测逻辑被布置为预测一个或多个预定属性，并且时钟生成逻辑响应来自预测逻辑的预测预定属性，以选择在执行访问期间要计时的哪个存储器单元，以及向该存储单元发出时钟信号。然后提供检查逻辑以确定由属性生成逻辑生成的预定属性是否与预测的预定属性一致，如果不是，则重新启动访问，在哪种情况下，时钟生成逻辑被设置为使用由属性生成逻辑确定的预定属性。这种方法可以实现对访问请求的高速处理，同时相对于其中多个存储器单元并行地推测地计时的现有技术系统实现显着的功率节省。

6. 发明授权

US06366978B1 Cache memory 有权
标题翻译：高速缓存存储器
公开(公告)号：US06366978B1
公开(公告)日：2002-04-02
申请号：US09434491
申请日：1999-11-05
申请人： Peter Guy Middleton , Michael Thomas Kilpatrick
发明人： Peter Guy Middleton , Michael Thomas Kilpatrick
IPC分类号： G06F1200
CPC分类号： G06F17/30982 , G06F12/0893 , G06F12/12 , G11C15/04
摘要： A cache memory system 22 is described in which a content addressable memory 24 and a cache RAM memory 28 are provided. Each content addressable storage row has an associated hit line 18 and an access enable line 12. An index decoder 46 is provided for controlling cache replacement and cache maintenance operations. The hit line 18 is used for passing both hit signals to the cache RAM 28 and select signals generated by the index decoder 46. A gate 36 operating under control of a multiplexer controller 44 controls this dual-use of the hit line 18 in dependence upon a selected mode of operation. In some embodiments a fast block transfer may be performed by loading data from a first address A into the cache memory 22. A match for the TAG value of the first address A could then be performed and the corresponding hit signal asserted and latched within a latch 43. Upon a subsequent cycle the latched hit signal can be passed to an access enable line 12 to permit a new TAG value corresponding to a second address B to be written to the content addressable memory 24. The cached data values from the first address A are now present within the cache memory system 22 associated with a TAG value of the second address B. The dirty bit may be set to ensure that writeback occurs when the data value is removed from the cache memory 22 thereby ensuring data integrity.
摘要翻译：描述了一种缓存存储器系统22，其中提供内容可寻址存储器24和高速缓存RAM存储器28。每个内容可寻址存储行具有相关联的命中线18和访问使能线12.提供索引解码器46用于控制高速缓存替换和高速缓存维护操作。命中线18用于将两个命中信号传送到高速缓存RAM28并选择索引解码器46产生的信号。在多路复用器控制器44的控制下操作的门36控制命中线18的这种双重用途，依赖于选定的操作模式。在一些实施例中，可以通过将数据从第一地址A加载到高速缓存存储器22中来执行快速块传输。然后可以执行对于第一地址A的TAG值的匹配，并且相应的命中信号被断言并锁存在锁存器在随后的周期中，锁存的命中信号可被传递到访问允许线12，以允许对应于第二地址B的新TAG值被写入内容可寻址存储器24.来自第一地址A的缓存的数据值现在存在于与第二地址B的TAG值相关联的高速缓冲存储器系统22内。可以设置脏位以确保当从高速缓冲存储器22移除数据值从而确保数据完整性时发生回写。

7. 发明授权

US07487367B2 Apparatus and method for managing access to a memory 有权
公开(公告)号：US07487367B2
公开(公告)日：2009-02-03
申请号：US10714521
申请日：2003-11-17
申请人： Lionel Belnet , Nicolas Chaussade , Simon Charles Watt , Peter Guy Middleton
发明人： Lionel Belnet , Nicolas Chaussade , Simon Charles Watt , Peter Guy Middleton
IPC分类号： H04L9/06 , G06F12/00
CPC分类号： G06F12/1491
摘要： The present invention provides a data processing apparatus and method for managing access to a memory within the data processing apparatus. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain, said processor being operable such that when executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode. Further, a memory is provided for storing data required by the processor, and consists of secure memory for storing secure data and non-secure memory for storing non-secure data. The memory further contains a non-secure table and a secure table, the non-secure table being within the non-secure memory and arranged to contain for each of a number of first memory regions an associated descriptor, and the secure table being within the secure memory and arranged to contain for each of a number of second memory regions an associated descriptor. When access to an item of data in the memory is required by the processor, the processor issues a memory access request, and a memory management unit is provided to perform one or more predetermined access control functions to control issuance of the memory access request to the memory. The memory management unit comprises an internal storage unit operable to store descriptors retrieved by the memory management unit from either the non-secure table or the secure table, and in accordance with the present invention the internal storage unit comprises a flag associated with each descriptor stored within the internal storage unit to identify whether that descriptor is from the non-secure table or the secure table. By this approach, when the processor is operating in a non-secure mode, the memory management unit is operable to perform the predetermined access control functions for the memory access request with reference to access control information derived from the descriptors in the internal storage unit retrieved from the non-secure table. In contrast, when the processor is operating in a secure mode, the memory management unit is operable to perform the predetermined access control functions for the memory access request with reference to access control information derived from the descriptors in the internal storage unit retrieved from the secure table. This approach enables different descriptors to be used for the control of accesses to memory in either the secure domain or the non-secure domain, whilst enabling such different descriptors to co-exist within the memory management unit's internal storage unit, thereby avoiding the requirement to flush the contents of such an internal storage unit when the operation of the processor changes from the secure domain to the non-secure domain, or vice versa.

8. 发明授权

US07171539B2 Apparatus and method for controlling access to a memory 有权
公开(公告)号：US07171539B2
公开(公告)日：2007-01-30
申请号：US10713454
申请日：2003-11-17
申请人： David Hennah Mansell , Michael Robert Nonweiler , Peter Guy Middleton
发明人： David Hennah Mansell , Michael Robert Nonweiler , Peter Guy Middleton
IPC分类号： G06F12/14
CPC分类号： G06F12/1491 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F12/145
摘要： The present invention provides a data processing apparatus and method for controlling access to a memory in the data processing apparatus. The apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory is operable to store data required by the processor and comprises secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required. At least one memory management unit is provided which is operable, upon receipt of the memory access request from the processor, to perform conversion of a virtual address specified by the memory access request to a physical address. A first set of tables is provided, each table in the first set containing a number of first descriptors, each first descriptor containing at least a virtual address portion and a corresponding intermediate address portion, and a second set of tables is also provided, with each table in the second set containing a number of second descriptors, each second descriptor containing at least an intermediate address portion and a corresponding physical address portion. The second set of tables are managed by the processor when operating in a privileged mode which is not a non-secure mode, and hence remains secure. The at least one memory management unit is then operable to cause predetermined tables in the first and second set to be referenced to enable the conversion of the virtual address specified by the memory access request to a physical address.

9. 发明授权

US06564301B1 Management of caches in a data processing apparatus 有权
标题翻译：管理数据处理设备中的高速缓存
公开(公告)号：US06564301B1
公开(公告)日：2003-05-13
申请号：US09348655
申请日：1999-07-06
申请人： Peter Guy Middleton
发明人： Peter Guy Middleton
IPC分类号： G01F1200
CPC分类号： G06F12/0804 , G06F12/0888
摘要： The data processing apparatus comprises a cache having a plurality of cache lines for storing data values retrieved from a plurality of memory regions, when a data value from a first memory region is stored in the cache and is subsequently updated within the cache by a new data value, the new data value is not transferred to memory until that new data value is removed from the cache. A marker is associated with each cache line and is settable to indicate that the data values stored in the corresponding cache line are from said first memory region. A protection unit for controlling the transfer of data values between the cache and the memory, is arranged, when said data values are to be loaded from the memory into a cache line of the cache, to determine whether said data values are from said first memory region and to cause the marker to be set accordingly. When the processor core outputs a new data value for storage, the cache is arranged to determine if the new data value is to replace a data value stored in a cache line of the cache, and if so to update the corresponding cache line with the new data value, and to apply predetermined criteria to determine whether to set an update identifier, such that when the new data value is subsequently removed from the cache it can be determined whether to transfer that new data value to the memory.
摘要翻译：当来自第一存储器区域的数据值被存储在高速缓存中并随后通过新的数据在高速缓存中更新时，数据处理装置包括具有多个高速缓存线的高速缓存，用于存储从多个存储区域检索的数据值值，新数据值不会传输到内存，直到从缓存中删除新的数据值。标记与每个高速缓存行相关联，并且可设置为指示存储在相应高速缓存行中的数据值来自所述第一存储器区域。当将所述数据值从存储器加载到高速缓存的高速缓存行中时，布置用于控制高速缓存和存储器之间的数据值传送的保护单元，以确定所述数据值是否来自所述第一存储器并使得标记被相应地设置。当处理器核心输出用于存储的新数据值时，高速缓存被布置为确定新数据值是否替换存储在高速缓存的高速缓存行中的数据值，并且如果是，则使用新的数据值更新相应的高速缓存行数据值，并且应用预定标准以确定是否设置更新标识符，使得当随后从高速缓存中移除新数据值时，可以确定是否将该新数据值传送到存储器。

10. 发明授权

US5860102A Cache memory circuit 失效
标题翻译：高速缓存存储器电路
公开(公告)号：US5860102A
公开(公告)日：1999-01-12
申请号：US715563
申请日：1996-09-18
申请人： Peter Guy Middleton
发明人： Peter Guy Middleton
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0859 , G06F12/0853
摘要： A cache memory circuit 36 is described which has a separate read bus 90 and write bus 98. When a given cache row is selected, then simultaneous read and write operations can take place to different words (W#0, W#1, W#2, W#3) within the cache row using the read bus and the write bus. The cache memory circuit 38 having this configuration is particularly suited for use as a write back cache. When a cache miss occurs causing the need for a cache row to be replaced, then the words are replaced starting with the word to which an attempted access triggered the cache miss and proceeding in ascending address order.
摘要翻译：描述了具有单独的读总线90和写总线98的高速缓冲存储器电路36.当选择给定的高速缓存行时，可以对不同的字（W＃0，W＃1，W＃ 2，W＃3）使用读总线和写总线。具有这种配置的高速缓冲存储器电路38特别适合用作回写高速缓存。当高速缓存未命中发生导致需要替换缓存行时，这些字将从尝试访问触发高速缓存未命中的单词开始替换，并按升序地址顺序进行。

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