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    • 1. 发明授权
    • Accessing memory units in a data processing apparatus
    • 访问数据处理设备中的存储器单元
    • US06826670B2
    • 2004-11-30
    • US10158105
    • 2002-05-31
    • Peter Guy MiddletonDavid Michael BullGary Campbell
    • Peter Guy MiddletonDavid Michael BullGary Campbell
    • G06F1200
    • G06F12/0888G06F12/0215Y02D10/13
    • The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access. Instead, prediction logic is arranged to predict the one or more predetermined attributes, and clock generation logic is responsive to the predictive predetermined attributes from the prediction logic to select which one of the memory units is to be clocked during performance of the access, and to issue a clock signal to that memory unit. Checking logic is then provided to determine whether the predetermined attributes generated by the attribute generation logic agree with the predicted predetermined attributes, and if not, to reinitiate the access, in which event the clock generation logic is arranged to reselect one of the memory units using the predetermined attributes as determined by the attribute generation logic. This approach enables high speed processing of access requests, whilst achieving significant power savings over prior art systems where multiple memory units are clocked speculatively in parallel.
    • 本发明涉及用于访问数据处理装置中的存储单元的技术。 数据处理装置包括用于存储数据值的多个存储器单元,用于发出指定对数据值对存储器单元进行访问的访问请求的处理器核心,以及用于执行由数据值指定的访问的存储器控​​制器 访问请求。 提供属性生成逻辑用于从访问请求确定一个或多个预定属性,以便在执行访问时验证哪个存储单元应被使用。 然而,存储器控制器不等待直到在开始访问之前由属性生成逻辑执行这样的确定。 相反,预测逻辑被布置为预测一个或多个预定属性,并且时钟生成逻辑响应来自预测逻辑的预测预定属性,以选择在执行访问期间要计时的哪个存储器单元,以及 向该存储单元发出时钟信号。 然后提供检查逻辑以确定由属性生成逻辑生成的预定属性是否与预测的预定属性一致,如果不是,则重新启动访问,在哪种情况下,时钟生成逻辑被设置为使用 由属性生成逻辑确定的预定属性。 这种方法可以实现对访问请求的高速处理,同时相对于其中多个存储器单元并行地推测地计时的现有技术系统实现显着的功率节省。
    • 8. 发明授权
    • Interrupt controller and method for handling interrupts
    • 中断控制器和处理中断的方法
    • US07805557B2
    • 2010-09-28
    • US11178586
    • 2005-07-12
    • Paul KimelmanGary CampbellSimon AxfordIan Field
    • Paul KimelmanGary CampbellSimon AxfordIan Field
    • G06F13/26
    • G06F13/26
    • An interrupt controller and method are provided for handling interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises pend logic for receiving interrupt requests generated by the plurality of interrupt sources, and for each interrupt request, determining whether to accept that interrupt request for handling by the interrupt controller. Interrupt handling logic then selects an interrupt request from amongst those interrupt requests accepted by the pend logic, and generates an indication of the interrupt routine to be executed by a processor to process that interrupt request. The pend logic is arranged, for each of the interrupt sources, to detect a transition of the associated interrupt request from an unset state to a set state, and to accept the interrupt request upon such detection. The pend logic also receives an exit signal indicating completion of the interrupt routine by the processor, and if the associated interrupt request is in the set state on receipt of the exit signal, re-accepts that interrupt request. By such an approach, the interrupt controller can automatically support both level interrupt requests and pulsed interrupt requests without the need for software configuration.
    • 提供了一种用于处理由多个中断源产生的中断请求的中断控制器和方法。 中断控制器包括用于接收由多个中断源产生的中断请求的后置逻辑,并且对于每个中断请求,确定是否接受该中断请求以由中断控制器处理。 然后中断处理逻辑从由挂起逻辑接受的那些中断请求中选择一个中断请求,并产生处理该中断请求的由处理器执行的中断程序的指示。 对于每个中断源,配置逻辑以检测相关联的中断请求从未设置状态到设置状态的转换,并且在这种检测时接受中断请求。 挂机逻辑还接收指示处理器完成中断程序的退出信号,如果相关联的中断请求在接收到退出信号时处于置位状态,则重新接受该中断请求。 通过这种方法,中断控制器可以自动支持电平中断请求和脉冲中断请求,而无需软件配置。
    • 9. 发明申请
    • Interrupt controller and method for handling interrupts
    • 中断控制器和处理中断的方法
    • US20070016710A1
    • 2007-01-18
    • US11178586
    • 2005-07-12
    • Paul KimelmanGary CampbellSimon AxfordIan Field
    • Paul KimelmanGary CampbellSimon AxfordIan Field
    • G06F13/26
    • G06F13/26
    • An interrupt controller and method are provided for handling interrupt requests generated by a plurality of interrupt sources. Th interrupt controller comprises pend logic for receiving interrupt requests generated by the plurality of interrupt sources, and for each interrupt request determining whether to accept that interrupt request for handling by the interrupt controller. Interrupt handling logic then selects an interrupt request from amongst those interrupt requests accepted by the pend logic, and generates an indication of the interrupt routine to be executed by a processor to process that interrupt request. The pend logic is arranged, for each of the interrupt sources, to detect a transition of the associated interrupt request from an unset state to a set state, and to accept the interrupt request upon such detection. The pend logic is also operable to receive an exit signal indicating completion of the interrupt routine by the processor, and if the associated interrupt request is in the set state on receipt of the exit signal, re-accepts that interrupt request. By such an approach, the interrupt controller can automatically support both level interrupt requests and pulsed interrupt requests without the need for software configuration.
    • 提供了一种用于处理由多个中断源产生的中断请求的中断控制器和方法。 中断控制器包括用于接收由多个中断源产生的中断请求的挂起逻辑,并且针对每个中断请求确定是否接受该中断请求以由中断控制器处理。 然后中断处理逻辑从由挂起逻辑接受的那些中断请求中选择一个中断请求,并产生处理该中断请求的由处理器执行的中断程序的指示。 对于每个中断源,配置逻辑以检测相关联的中断请求从未设置状态到设置状态的转换,并且在这种检测时接受中断请求。 后端逻辑还可操作以接收指示处理器完成中断程序的退出信号,并且如果相关联的中断请求在接收到退出信号时处于置位状态,则重新接受该中断请求。 通过这种方法,中断控制器可以自动支持电平中断请求和脉冲中断请求,而无需软件配置。