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1. 发明授权

US07213095B2 Bus transaction management within data processing systems 有权
标题翻译：数据处理系统内的总线事务管理
公开(公告)号：US07213095B2
公开(公告)日：2007-05-01
申请号：US10862884
申请日：2004-06-08
申请人： Peter Guy Middleton , David John Gwilt , Ian Victor Devereux , Bruce James Mathewson , Antony John Harris , Richard Roy Grisenthwaite
发明人： Peter Guy Middleton , David John Gwilt , Ian Victor Devereux , Bruce James Mathewson , Antony John Harris , Richard Roy Grisenthwaite
IPC分类号： G06F13/36
CPC分类号： G06F13/1631
摘要： A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.
摘要翻译：数据处理系统具有总线，该总线具有分开的写通道W和读通道R，通过该通道进行总线交易。总线事务缓冲器34设置在总线结构内以缓冲写入请求，特别是为了减轻与相对较慢的总线从站相关联的问题。总线事务缓冲器34响应于与写入请求相关联的存储器地址和通过它们的读取请求，以将它们识别到相同存储器地址或者在预定范围内的存储器地址，以便确保那些交易，读取以遵循写入，或者在写入缓冲写入数据值之后满足读取，然后刷新读取请求，使其不到达其最终目的地。

2. 发明授权

US06904500B2 Cache controller 有权
标题翻译：缓存控制器
公开(公告)号：US06904500B2
公开(公告)日：2005-06-07
申请号：US10207386
申请日：2002-07-30
申请人： David John Gwilt , Richard Roy Grisenthwaite
发明人： David John Gwilt , Richard Roy Grisenthwaite
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0859
摘要： A cache controller operable to control a cache comprising cache lines, each being operable to store data words and validity information indicating that all data words within that cache line are valid. The cache controller comprises a linefill mechanism operable to write data words to a cache line, to provide an indication when each of the data words has been written to the cache and to set the validity information when all data words in the cache line have been written; and a data word accessing mechanism, responsive to a request to access a data word during a linefill operation prior to the validity information being set, to determine from the indication provided by the linefill mechanism whether the data word to be accessed has already been written during the linefill operation and, if so, to provide a signal indicating that the data word is accessible.
摘要翻译：一种高速缓存控制器，可操作用于控制包括高速缓存行的高速缓存，每个高速缓存行可操作以存储指示该高速缓存行内的所有数据字有效的数据字和有效信息。高速缓冲存储器控制器包括一个可以将数据字写入高速缓存行的线性填充机构，当每个数据字被写入高速缓存时提供一个指示，并且当高速缓存行中的所有数据字都被写入时设置有效性信息 ; 以及数据字访问机制，响应于在设置有效性信息之前的行填充操作期间访问数据字的请求，根据由行填充机制提供的指示来确定是否已经写入要访问的数据字如果是，则提供指示数据字可访问的信号。

3. 发明授权

US06532553B1 Debugging data processing systems 有权
标题翻译：调试数据处理系统
公开(公告)号：US06532553B1
公开(公告)日：2003-03-11
申请号：US09407846
申请日：1999-09-29
申请人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
发明人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
IPC分类号： H02H305
CPC分类号： G06F11/3636 , G06F9/30003 , G06F9/3005
摘要： A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.
摘要翻译：提供了具有主处理器4和协处理器26的数据处理系统。当处于调试模式时，向主处理器4和协处理器26提供不同的指令。协处理器26被提供有协处理器调试数据生成指令（MCR），而主处理器4被提供有主处理器数据捕获指令（LDR）。协处理器26通过控制表示数据处理装置2的状态的调试数据来响应MCR指令，数据处理装置2将被放置在数据总线24上，从LDR指令的控制下由主处理器4读取数据总线24。

4. 发明授权

US06959351B2 Handling of a multi-access instruction in a data processing apparatus 有权
公开(公告)号：US06959351B2
公开(公告)日：2005-10-25
申请号：US10405495
申请日：2003-04-03
申请人： David John Gwilt , Bruce Mathewson
发明人： David John Gwilt , Bruce Mathewson
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/38 , G06F9/46 , G06F12/00 , G06F13/00 , G06F13/16
CPC分类号： G06F9/30043 , G06F9/3824
摘要： The present invention provides a data processing apparatus and method for handling a multi-access instruction of the type which specifies that an access request of a first type and an access request of a second type should be performed without any intervening accesses taking place. The data processing apparatus has a processor operable to execute instructions, and a first master logic unit and a second master logic unit operable to process access requests generated during execution of those instructions. The access requests specify accesses to a slave device, with the first master logic unit being operable to access the slave device via a first bus, and the second master logic unit being operable to access the slave device via a second bus. Routing logic is provided to determine, for each access request, which master logic unit is to process that access request, the first master logic unit being arranged to process access requests of the first type, and the second master logic unit being arranged to process access requests of the second type. The routing logic is arranged in the event of execution of the multi-access instruction to cause both the access request of the first type and the access request of the second type specified by the multi-access instruction to be processed by the first master logic unit. Further, the first master logic unit is arranged, when processing the access requests of the multi-access instruction, to issue a lock signal which is used to ensure that the first master logic unit is granted sole access to the slave device whilst the first master logic unit is processing the access requests of the first and second type. This approach enables the benefits of providing a separate master logic unit for accesses of the first type and a separate master logic unit for accesses of the second type to be realised, whilst enabling the above-described multi-access instruction to be executed in the desired manner, i.e. by ensuring that the access requests of the first and second type specified by the multi-access instruction are performed without any intervening accesses taking place.

5. 发明授权

US07181556B2 Transaction request servicing mechanism 有权
标题翻译：交易请求服务机制
公开(公告)号：US07181556B2
公开(公告)日：2007-02-20
申请号：US10743537
申请日：2003-12-23
申请人： David John Gwilt
发明人： David John Gwilt
IPC分类号： G06F13/00 , G06F15/16 , H04L12/28 , G06F13/36
CPC分类号： G06F13/36
摘要： A data processing apparatus comprises a master device 150, 160, 170, 180, a slave device 110, 120, 130 and a communication bus 140 via which transaction requests are passed from master to slave. A transaction annotator of the master device generates transaction identifiers having a master identifier portion and a priority request portion. The slave device determines an order of servicing of transaction requests in dependence upon transaction ordering requests at least partially derived from the master identifier portions and in dependence upon priority values specified in the priority request portions.
摘要翻译：数据处理装置包括主设备150,160,170,180，从设备110,120,130和通信总线140，通过该总线140，事务请求从主设备传送到从设备。主设备的事务注释器产生具有主标识符部分和优先权请求部分的事务标识符。从设备根据至少部分地从主标识符部分导出并且依赖于优先级请求部分中指定的优先级值的事务排序请求来确定事务请求的服务顺序。

6. 发明申请

US20080235707A1 Data processing apparatus and method for performing multi-cycle arbitration 有权
标题翻译：用于执行多周期仲裁的数据处理装置和方法
公开(公告)号：US20080235707A1
公开(公告)日：2008-09-25
申请号：US12076391
申请日：2008-03-18
申请人： David John Gwilt , Graeme Leslie Ingram
发明人： David John Gwilt , Graeme Leslie Ingram
IPC分类号： G06F9/46
CPC分类号： G06F13/364 , G06F13/1615
摘要： A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states. For a new multi-cycle arbitration operation to be performed by the arbitration circuitry, the filter circuitry selects one of the filter states that has not been selected for any other multi-cycle arbitration operation already in progress within the pipeline states of the arbitration circuitry. Then, it determines as candidate access requests for the new multi-cycle arbitration operation those access requests that are seeking to access a resource associated with the selected filter state. Such an approach allows efficient multi-cycle arbitration to take place even where the resources may have inter-access timing parameters associated therewith which prevent them from being able to receive access requests every clock cycle.
摘要翻译：提供了一种用于在寻求访问共享公共访问路径的多个资源的多个访问请求之间进行仲裁的数据处理装置和方法。至少一个逻辑元件发出请求访问资源的访问请求，并且每个访问请求标识要访问哪个资源。仲裁电路执行多循环仲裁操作，以在通过公共访问路径传递的多个访问请求之间进行仲裁，仲裁电路具有多个流水线级，以允许相应的多个多周期仲裁操作在任何一次。提供了具有多个滤波器状态的滤波器电路，滤波器状态的数量取决于仲裁电路的流水线级数，并且每个资源与滤波器状态之一相关联。对于要由仲裁电路执行的新的多周期仲裁操作，滤波器电路选择在仲裁电路的流水线状态内已经进行的任何其他多循环仲裁操作尚未被选择的滤波器状态之一。然后，它确定新的多周期仲裁操作的候选访问请求，寻求访问与所选择的过滤状态相关联的资源的那些访问请求。即使在资源可能具有与其相关联的访问间定时参数的情况下，这种方法也允许有效的多循环仲裁，这阻碍了它们在每个时钟周期内能够接收访问请求。

7. 发明授权

US08667199B2 Data processing apparatus and method for performing multi-cycle arbitration 有权
标题翻译：用于执行多周期仲裁的数据处理装置和方法
公开(公告)号：US08667199B2
公开(公告)日：2014-03-04
申请号：US12076391
申请日：2008-03-18
申请人： David John Gwilt , Graeme Leslie Ingram
发明人： David John Gwilt , Graeme Leslie Ingram
IPC分类号： G06F12/00
CPC分类号： G06F13/364 , G06F13/1615
摘要： A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states. For a new multi-cycle arbitration operation to be performed by the arbitration circuitry, the filter circuitry selects one of the filter states that has not been selected for any other multi-cycle arbitration operation already in progress within the pipeline states of the arbitration circuitry. Then, it determines as candidate access requests for the new multi-cycle arbitration operation those access requests that are seeking to access a resource associated with the selected filter state. Such an approach allows efficient multi-cycle arbitration to take place even where the resources may have inter-access timing parameters associated therewith which prevent them from being able to receive access requests every clock cycle.
摘要翻译：提供了一种用于在寻求访问共享公共访问路径的多个资源的多个访问请求之间进行仲裁的数据处理装置和方法。至少一个逻辑元件发出请求访问资源的访问请求，并且每个访问请求标识要访问哪个资源。仲裁电路执行多循环仲裁操作，以在通过公共访问路径传递的多个访问请求之间进行仲裁，仲裁电路具有多个流水线级，以允许相应的多个多周期仲裁操作在任何一次。提供了具有多个滤波器状态的滤波器电路，滤波器状态的数量取决于仲裁电路的流水线级数，并且每个资源与滤波器状态之一相关联。对于要由仲裁电路执行的新的多周期仲裁操作，滤波器电路选择在仲裁电路的流水线状态内已经进行的任何其他多循环仲裁操作尚未被选择的滤波器状态之一。然后，它确定新的多周期仲裁操作的候选访问请求，寻求访问与所选择的过滤状态相关联的资源的那些访问请求。即使在资源可能具有与其相关联的访问间定时参数的情况下，这种方法也允许有效的多循环仲裁，这阻碍了它们在每个时钟周期内能够接收访问请求。

8. 发明授权

US07603496B2 Buffering data during data transfer through a plurality of channels 有权
标题翻译：通过多个通道在数据传输期间缓冲数据
公开(公告)号：US07603496B2
公开(公告)日：2009-10-13
申请号：US11337111
申请日：2006-01-23
申请人： Christopher Edwin Wrigley , David John Gwilt
发明人： Christopher Edwin Wrigley , David John Gwilt
IPC分类号： G06F3/00 , G06F13/36
CPC分类号： G06F5/065 , G06F5/14 , G06F2205/064
摘要： A buffer is disclosed for storing data being transferred using a plurality of control channels, a data item of said data being transferred between a data source and a data destination using one of said plurality of control channels, said buffer comprising: a data input port operable to receive said data being transferred using said plurality of control channels; a data output port operable to output data to be transferred using said plurality of control channels; and a data store operable to store data received from said data input port prior to it being output by said data output port, said data store comprising a plurality of storage locations each operable to store a data item, said storage locations being arranged in groups, a storage location being allocated to a group in dependence on the control channel that a data item that it stores is received from, such that each group comprises storage locations storing data items received from a same one of said plurality of control channels. Free storage locations are not allocated to any of the plurality of groups, so that new data items received can be stored in any of the free storage locations, these locations then being allocated to the group corresponding to the channel being used.
摘要翻译：公开了一种用于存储使用多个控制信道传输的数据的缓冲器，所述数据的数据项使用所述多个控制信道之一在数据源和数据目的地之间传送，所述缓冲器包括：可操作的数据输入端口接收使用所述多个控制信道传输的所述数据; 数据输出端口，其可操作以使用所述多个控制信道输出要传送的数据; 以及数据存储器，用于在由所述数据输出端口输出之前存储从所述数据输入端口接收的数据，所述数据存储器包括多个存储位置，每个存储位置可操作以存储数据项，所述存储位置被分组排列，存储位置根据控制信道被分配给组，其中存储的数据项被接收，使得每个组包括存储从所述多个控制信道中的相同一个控制信道接收的数据项的存储位置。空闲存储位置不分配给多个组中的任一组，使得接收到的新数据项可以存储在任何空闲存储位置中，然后这些位置被分配给与所使用的信道相对应的组。

9. 发明授权

US09225938B2 Video conferencing systems 有权
标题翻译：视频会议系统
公开(公告)号：US09225938B2
公开(公告)日：2015-12-29
申请号：US14126802
申请日：2012-06-06
申请人： David John Gwilt , Alexander Edward Nancekievill
发明人： David John Gwilt , Alexander Edward Nancekievill
IPC分类号： H04N7/15 , H04M7/00 , H04N7/14 , H04M3/56
CPC分类号： H04N7/15 , H04M3/567 , H04M3/568 , H04M7/0027 , H04M7/0039 , H04M2201/22 , H04M2201/50 , H04N7/147
摘要： We describe a system for automatic setup of an audio/computer teleconference. The system comprises node units each having a phone connection, a telephone network connection, at least one computer network connection; and a system control server. The node unit comprises code to: transmit an outgoing audio announce message into a potential conference call via said telephone network audio connection, identifying the node unit; receive via the network audio connection an incoming audio announce message from a conference call to which the node unit is already connected; determine from the incoming message, an identifier for a remote node unit connecting to the conference call; and transmit to the server, via the computer network, identifiers for the local and remote node units. The server comprises code to: receive the node unit identifiers and provide computer equipment connection data to computer equipment at node.
摘要翻译：我们描述一个自动设置音频/电脑电话会议的系统。该系统包括各自具有电话连接，电话网络连接，至少一个计算机网络连接的节点单元; 和系统控制服务器。节点单元包括用于经由所述电话网络音频连接将出局音频通告消息发送到潜在电话会议的代码，识别节点单元; 通过网络音频连接接收来自节点单元已经连接到的电话会议的传入音频通知消息; 从传入消息中确定连接到电话会议的远程节点单元的标识符; 并通过计算机网络向服务器发送本地和远程节点单元的标识符。服务器包括以下代码：接收节点单元标识符，并向节点处的计算机设备提供计算机设备连接数据。

10. 发明授权

US09088695B2 Video conferencing systems 有权
标题翻译：视频会议系统
公开(公告)号：US09088695B2
公开(公告)日：2015-07-21
申请号：US14108039
申请日：2013-12-16
申请人： David John Gwilt , Alexander Edward Nancekievill
发明人： David John Gwilt , Alexander Edward Nancekievill
IPC分类号： H04M11/00 , H04N7/15 , H04M7/00 , H04N7/14 , H04M3/56
CPC分类号： H04N7/15 , H04M3/567 , H04M3/568 , H04M7/0027 , H04M7/0039 , H04M2201/22 , H04M2201/50 , H04N7/147
摘要： We describe a method of synchronizing a teleconference comprising audio carried on a telephone network and a digital data stream carried on a computer network. Audio at a first node is characterized to determine audio characterizing data. A digital data stream for the teleconference is also input at the first node and the audio characterizing data is inserted into the digital data stream and forwarded over the network. The audio and digital data streams are received separately at a second node of the system, and the audio characterizing data is extracted from the digital data stream and processed in conjunction with the received audio to determine a first-second node time offset. The audio and digital data streams are then synchronizing by adjusting, for example, a relative time delay of the received audio and digital streams at the second node responsive to the determined time offset.
摘要翻译：我们描述了一种同步电话会议的方法，其包括电话网络上承载的音频和在计算机网络上承载的数字数据流。第一节点处的音频的特征在于确定音频表征数据。用于电话会议的数字数据流也被输入到第一节点，并且音频表征数据被插入到数字数据流中并通过网络转发。音频和数字数据流在系统的第二个节点被单独接收，并且从数字数据流中提取音频表征数据，并结合所接收的音频进行处理以确定第一秒的节点时间偏移量。音频和数字数据流然后通过例如响应于所确定的时间偏移调整接收到的音频和第二节点上的数字流的相对时间延迟来同步。

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