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1. 发明授权

US5619662A Memory reference tagging 失效
标题翻译：内存引用标记
公开(公告)号：US5619662A
公开(公告)日：1997-04-08
申请号：US289613
申请日：1994-08-12
申请人： Simon C. Steely, Jr. , David J. Sager , David B. Fite, Jr.
发明人： Simon C. Steely, Jr. , David J. Sager , David B. Fite, Jr.
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3863 , G06F9/3012 , G06F9/30141 , G06F9/322 , G06F9/3802 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由该组指令馈送的指令调度器，以从指令处理器重新排序指令集的发布。映射的寄存器操作数字段在指令发布之前与重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

2. 发明授权

US5519841A Multi instruction register mapper 失效
标题翻译：多指令寄存器映射器
公开(公告)号：US5519841A
公开(公告)日：1996-05-21
申请号：US974776
申请日：1992-11-12
申请人： David J. Sager , Simon C. Steely, Jr. , David B. Fite, Jr.
发明人： David J. Sager , Simon C. Steely, Jr. , David B. Fite, Jr.
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/34
CPC分类号： G06F9/3863 , G06F9/32 , G06F9/3806 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857
摘要： A pipelined processor includes an instruction unit including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令单元，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由该组指令馈送的指令调度器，以从处理器重新排序指令集的发布。映射的寄存器操作数字段在指令发布之前与重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

3. 发明授权

US5828874A Past-history filtered branch prediction 失效
标题翻译：过去历史过滤分支预测
公开(公告)号：US5828874A
公开(公告)日：1998-10-27
申请号：US626868
申请日：1996-06-05
申请人： Simon C. Steely, Jr. , David J. Sager
发明人： Simon C. Steely, Jr. , David J. Sager
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/30043 , G06F9/3012 , G06F9/30134 , G06F9/30141 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A branch prediction apparatus includes a predicted past history device, and a a branch prediction device. The predicted past history device is operable to receive an indication of a branch instruction and to output a pattern of past predictions of branch directions for the indicated branch instruction. The pattern of past predictions includes at least one prediction of a branch direction for which the correctness of the prediction has not been determined The branch prediction device is operable to receive the pattern of past predictions of branch directions for the indicated branch instruction and to output a predicted branch direction for the indicated branch instruction based on the received pattern of past predictions.
摘要翻译：分支预测装置包括预测的过去历史装置和分支预测装置。预测的过去历史装置可操作以接收分支指令的指示并输出针对所指示的分支指令的分支方向的过去预测的模式。过去预测的模式包括尚未确定预测的正确性的分支方向的至少一个预测。分支预测装置可操作以接收针对所指示的分支指令的分支方向的过去预测的模式，并输出基于接收到的过去预测模式，为指示的分支指令预测分支方向。

4. 发明授权

US5581719A Multiple block line prediction 失效
标题翻译：多块线预测
公开(公告)号：US5581719A
公开(公告)日：1996-12-03
申请号：US401656
申请日：1995-03-10
申请人： Simon C. Steely, Jr. , David J. Sager
发明人： Simon C. Steely, Jr. , David J. Sager
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3863 , G06F9/30054 , G06F9/3012 , G06F9/30141 , G06F9/3806 , G06F9/3814 , G06F9/3848
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由所述指令组馈送的指令调度器，以从所述指令处理器重新排序所述指令集的发布。映射的寄存器操作数字段在指令发布之前与所述重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

5. 发明授权

US5564118A Past-history filtered branch prediction 失效
标题翻译：过去历史过滤分支预测
公开(公告)号：US5564118A
公开(公告)日：1996-10-08
申请号：US352291
申请日：1994-12-08
申请人： Simon C. Steely, Jr. , David J. Sager , William B. Noyce
发明人： Simon C. Steely, Jr. , David J. Sager , William B. Noyce
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/30043 , G06F9/3012 , G06F9/30134 , G06F9/30141 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由所述指令组馈送的指令调度器，以从所述指令处理器重新排序所述指令集的发布。映射的寄存器操作数字段在指令发布之前与所述重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

6. 发明授权

US5003459A Cache memory system 失效
标题翻译：缓存存储系统
公开(公告)号：US5003459A
公开(公告)日：1991-03-26
申请号：US176595
申请日：1988-04-01
申请人： Raj K. Ramanujan , Simon C. Steely, Jr. , Peter J. Bannon , David J. Sager
发明人： Raj K. Ramanujan , Simon C. Steely, Jr. , Peter J. Bannon , David J. Sager
IPC分类号： G06F12/10
CPC分类号： G06F12/1045
摘要： The invention is directed to a cache memory system in a data processor including a virtual cache memory, a physical cache memory, a virtual to physical translation buffer, a physical to virtual backmap, an Old-PA pointer and a lockout register. The backmap implements invalidates by clearing the valid flags in virtual cache memory. The Old-PA pointer indicates the backmap entry to be invalidated after a reference misses in the virtual cache. The physical address for data written to virtual cache memory is entered to Old-PA pointer by the translation buffer. The lockout register arrests all references to data which may have synonyms in virtual cache memory. The backmap is also used to invalidate any synonyms.
摘要翻译：本发明涉及包括虚拟高速缓冲存储器，物理高速缓冲存储器，虚拟到物理转换缓冲器，物理到虚拟背景图，旧PA指针和锁定寄存器的数据处理器中的高速缓冲存储器系统。反向映射通过清除虚拟高速缓存中的有效标志来实现无效。 Old-PA指针指示在虚拟缓存中的引用未命中之后，将无效的背景条目。写入虚拟高速缓冲存储器的数据的物理地址由转换缓冲区输入到旧PA指针。锁定寄存器阻止对虚拟高速缓冲存储器中可能具有同义词的数据的所有引用。背景图也用于使任何同义词无效。

7. 发明授权

US5283873A Next line prediction apparatus for a pipelined computed system 失效
标题翻译：用于流水线计算系统的下一行预测装置
公开(公告)号：US5283873A
公开(公告)日：1994-02-01
申请号：US546364
申请日：1990-06-29
申请人： Simon C. Steely, Jr. , David J. Sager
发明人： Simon C. Steely, Jr. , David J. Sager
IPC分类号： G06F9/38 , G06F9/34 , G06F9/40
CPC分类号： G06F9/3806
摘要： A next line prediction mechanism for predicting a next instruction index to an instruction cache of a computer pipeline, has a latency equal to the cycle time of the instruction cache to maximize the instruction bandwidth out of the instruction cache. The instruction cache outputs a block of instructions with each fetch initiated by a next instruction index provided by the line prediction mechanism. The instructions of the block are processed in parallel for instruction decode and branch prediction to maintain a high rate of instruction flow through the pipeline.
摘要翻译：用于预测对计算机流水线的指令高速缓存的下一个指令索引的下一行预测机制具有等于指令高速缓冲存储器的循环时间的等待时间，以使指令高速缓存中的指令带宽最大化。指令高速缓存输出由行预测机制提供的下一指令索引发起的每次提取的指令块。块的指令被并行处理，用于指令解码和分支预测，以保持高流量的指令流经管线。

8. 发明授权

US5197132A Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery 失效
标题翻译：具有包含顺序列表的寄存器映射系统的寄存器映射系统，用于在精确的分支后恢复中预测循环中的寄存器
公开(公告)号：US5197132A
公开(公告)日：1993-03-23
申请号：US546411
申请日：1990-06-29
申请人： Simon C. Steely, Jr. , David J. Sager
发明人： Simon C. Steely, Jr. , David J. Sager
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3863
摘要： A register map having a free list of available physical locations in a register file, a log containing a sequential listing of logical registers changed during a predetermined number of cycles, a back-up map associating the logical registers with corresponding physical homes at a back-up point in a computer pipeline operation and a predicted map associating the logical registers with corresponding physical homes at a current point in the computer pipeline operation. A set of valid bits is associated with the maps to indicate whether a particular logical register is to be taken from the back-up map or the predicted map indication of a corresponding physical home. The valid bits can be "flash cleared" in a single cycle to back-up the computer pipeline to the back-up point during a trap event.

9. 发明授权

US5179673A Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline 失效
标题翻译：使用环形缓冲器的SUBROUTINE返回预测机制，并与实际地址进行比较以预测地址以验证或冲洗管道
公开(公告)号：US5179673A
公开(公告)日：1993-01-12
申请号：US451943
申请日：1989-12-18
申请人： Simon C. Steely, Jr. , David J. Sager
发明人： Simon C. Steely, Jr. , David J. Sager
IPC分类号： G06F9/32 , G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/322 , G06F9/4426
摘要： A method and arrangement for producing a predicted subroutine return address in response to entry of a subroutine return instruction in a computer pipeline that has a ring pointer counter and a ring buffer coupled to the ring pointer counter. The ring pointer counter contains a ring pointer that is changed when either a subroutine call instruction or return instruction enters the computer pipeline. The ring buffer has buffer locations which store a value present at its input into the buffer location pointed to by the ring pointer when a subroutine call instruction enters the pipeline. The ring buffer provides a value from the buffer location pointed to by the ring pointer when a subroutine return instruction enters the computer pipeline, this provided value being the predicted subroutine return address.

10. 发明申请

US20140281424A1 TRACKING CONTROL FLOW OF INSTRUCTIONS 有权
标题翻译：跟踪指令的控制流程
公开(公告)号：US20140281424A1
公开(公告)日：2014-09-18
申请号：US13834049
申请日：2013-03-15
申请人： Jayaram Bobba , Ruchira Sasanka , Jeffrey J. Cook , Abhinav Das , Arvind Krishnaswamy , David J. Sager , Jason M. Agron
发明人： Jayaram Bobba , Ruchira Sasanka , Jeffrey J. Cook , Abhinav Das , Arvind Krishnaswamy , David J. Sager , Jason M. Agron
IPC分类号： G06F9/30
CPC分类号： G06F9/3005 , G06F8/433 , G06F11/0715 , G06F11/0721 , G06F11/076 , G06F11/3466
摘要： A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.
摘要翻译：公开了一种用于跟踪应用程序中的指令的控制流程并基于应用程序中的指令的控制流程执行处理设备的一个或多个优化的机制。生成控制流数据以指示应用程序中的指令块的控制流程。控制流数据可以包括指示是否可以针对不同的指令块执行优化的注释。控制流数据还可以用于跟踪指令的执行以确定指令块中的指令是否被分配给处理器的线程，进程和/或执行核心，并且确定错误是否具有在执行指令期间发生。

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