专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070023909A1 System including self-assembled interconnections 有权
标题翻译：系统包括自组装互连
公开(公告)号：US20070023909A1
公开(公告)日：2007-02-01
申请号：US11191566
申请日：2005-07-27
申请人： David Fork , Thomas Hantschel , Michael Chabinyc
发明人： David Fork , Thomas Hantschel , Michael Chabinyc
IPC分类号： H01L23/48
CPC分类号： H05K3/32 , B82Y30/00 , H01L2924/0002 , H05K3/102 , H05K3/321 , H05K3/325 , H05K2201/0209 , H05K2201/0239 , H05K2201/0266 , H05K2201/0347 , H05K2201/0367 , H05K2201/083 , H01L2924/00
摘要： A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.
摘要翻译：描述形成自组装互连结构的方法。在该方法中，接触垫表面和溶液中的颗粒被聚集在一起。颗粒被选择成使得颗粒粘附到接触垫表面。接触的形成通过将相对的接触压入颗粒中而完成，使得经由相对的接触垫和基板表面接触垫之间的颗粒形成电连接。所描述的自组装互连结构在显示器件制造中特别有用。

2. 发明申请

US20070023907A1 Self-assembled interconnection particles 有权
标题翻译：自组装互连颗粒
公开(公告)号：US20070023907A1
公开(公告)日：2007-02-01
申请号：US11191435
申请日：2005-07-27
申请人： David Fork , Thomas Hantschel , Michael Chabinyc
发明人： David Fork , Thomas Hantschel , Michael Chabinyc
IPC分类号： H01L23/48
CPC分类号： H05K3/321 , B82Y30/00 , H01L21/4853 , H01L21/6835 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/29 , H01L24/83 , H01L24/90 , H01L2224/03912 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/11332 , H01L2224/11334 , H01L2224/11442 , H01L2224/1147 , H01L2224/1148 , H01L2224/1182 , H01L2224/11901 , H01L2224/13022 , H01L2224/13078 , H01L2224/13144 , H01L2224/1357 , H01L2224/136 , H01L2224/29101 , H01L2224/29399 , H01L2224/81801 , H01L2224/838 , H01L2924/00013 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H05K3/102 , H05K2203/122 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.
摘要翻译：描述形成自组装互连结构的方法。在该方法中，接触垫表面和溶液中的颗粒被聚集在一起。颗粒被选择成使得颗粒粘附到接触垫表面。接触的形成通过将相对的接触压入颗粒中而完成，使得经由相对的接触垫和基板表面接触垫之间的颗粒形成电连接。所描述的自组装互连结构在显示器件制造中特别有用。

3. 发明申请

US20070023908A1 Method of fabricating self-assembled electrical interconnections 有权
标题翻译：制造自组装电气互连的方法
公开(公告)号：US20070023908A1
公开(公告)日：2007-02-01
申请号：US11191436
申请日：2005-07-27
申请人： David Fork , Thomas Hantschel , Michael Chabinyc
发明人： David Fork , Thomas Hantschel , Michael Chabinyc
IPC分类号： H01L23/48
CPC分类号： H05K3/32 , B82Y30/00 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05556 , H01L2224/11015 , H01L2224/11332 , H01L2224/11334 , H01L2224/1147 , H01L2224/13005 , H01L2224/13019 , H01L2224/13078 , H01L2224/13082 , H01L2224/131 , H01L2224/1319 , H01L2224/13561 , H01L2224/13582 , H01L2224/13644 , H01L2224/13655 , H01L2924/14 , H05K3/102 , H05K3/321 , H05K3/325 , H05K2201/0209 , H05K2201/0239 , H05K2201/0266 , H05K2201/0347 , H05K2201/0367 , H05K2201/083 , H01L2924/00014 , H01L2924/00012 , H01L2924/207 , H01L2924/00
摘要： A method of forming a self-assembled interconnect structure is described. In the method, a contact pad surface and particles in a solution are brought together. The particles are selected such that they the particles adhere to the contact pad surface. Formation of a contact is completed by pressing an opposite contact into the particles such that an electrical connection is formed via the particles between the opposite contact pad and the substrate surface contact pad. The described self-assembled interconnect structure is particularly useful in display device fabrication.
摘要翻译：描述形成自组装互连结构的方法。在该方法中，接触垫表面和溶液中的颗粒被聚集在一起。颗粒被选择成使得颗粒粘附到接触垫表面。接触的形成通过将相对的接触压入颗粒中而完成，使得经由相对的接触垫和基板表面接触垫之间的颗粒形成电连接。所描述的自组装互连结构在显示器件制造中特别有用。

4. 发明授权

US09882108B2 Nanostructured layers of thermoelectric materials 有权
公开(公告)号：US09882108B2
公开(公告)日：2018-01-30
申请号：US15254412
申请日：2016-09-01
申请人： Jeffrey J. Urban , Jared Lynch , Nelson Coates , Jason Forster , Ayaskanta Sahu , Michael Chabinyc , Boris Russ
发明人： Jeffrey J. Urban , Jared Lynch , Nelson Coates , Jason Forster , Ayaskanta Sahu , Michael Chabinyc , Boris Russ
IPC分类号： H01L35/16 , H01L35/34 , H01L35/02 , C01B19/00 , C09D1/00 , C09D5/26 , C09D5/24
CPC分类号： H01L35/16 , C01B19/007 , C01P2004/16 , C01P2004/64 , C01P2006/40 , C09D1/00 , C09D5/24 , C09D5/26 , H01L35/02 , H01L35/34
摘要： This disclosure provides systems, methods, and apparatus related to thermoelectric materials. In one aspect, a method includes providing a plurality of nanostructures. The plurality of nanostructures comprise a thermoelectric material, with each nanostructure of the plurality of nanostructures having first ligands disposed on a surface of the nanostructure. The plurality of nanostructures is mixed with a solution containing second ligands and a ligand exchange process occurs in which the first ligands disposed on the plurality of nanostructures are replaced with the second ligands. The plurality of nanostructures is deposited on a substrate to form a layer. The layer is thermally annealed.

5. 发明申请

US20120322214A1 METHOD AND STRUCTURE FOR ESTABLISHING CONTACTS IN THIN FILM TRANSISTOR DEVICES 有权
标题翻译：在薄膜晶体管器件中建立接触的方法和结构
公开(公告)号：US20120322214A1
公开(公告)日：2012-12-20
申请号：US13594507
申请日：2012-08-24
申请人： Jürgen H. Daniel , Ana Claudia Arias , Michael Chabinyc
发明人： Jürgen H. Daniel , Ana Claudia Arias , Michael Chabinyc
IPC分类号： H01L21/336
CPC分类号： H01L51/0558 , H01L29/1606 , H01L29/78684 , H01L29/7869 , H01L51/0003 , H01L51/0037 , H01L51/052 , H01L51/0541 , H01L51/0545 , H01L51/0562
摘要： The roughness and structural height of printed metal lines is used to pin a fluid. This fluid deposits a top contact material which is connected to the bottom printed contacts through pinholes in the hydrophobic polymer layer. This results in a sandwich-like contact structure achieved in a self-aligned deposition process and having improved source-drain contact for all-additive printed circuits. In one form, the present technique is used for thin film transistor applications, but it may be applied to electrodes in general.
摘要翻译：印刷金属线的粗糙度和结构高度用于固定流体。该流体通过疏水性聚合物层中的针孔沉积顶部接触材料，其通过针孔连接到底部印刷的触点。这导致在自对准沉积工艺中实现的夹层状接触结构，并且具有改进的用于全部添加印刷电路的源极 - 漏极接触。在一种形式中，本技术用于薄膜晶体管应用，但通常可以应用于电极。

6. 发明授权

US07384568B2 Method of forming a darkfield etch mask 失效
标题翻译：形成暗场蚀刻掩模的方法
公开(公告)号：US07384568B2
公开(公告)日：2008-06-10
申请号：US11394438
申请日：2006-03-31
申请人： William Wong , Scott Limb , Beverly Russo , Michael Chabinyc , Rene Lujan
发明人： William Wong , Scott Limb , Beverly Russo , Michael Chabinyc , Rene Lujan
IPC分类号： B44C1/22 , C03C25/68 , C03C15/00 , C23F1/00
CPC分类号： B44C1/22 , H01L27/1292 , H01L29/4908
摘要： Susceptibility of darkfield etch masks (majority of the mask area is opaque) to pinhole defects, transferred pattern, non-uniformity, etc. due to ejector dropout or drop misdirection, and long duty cycles due to large-area coverage, when using digital lithography (or print patterning) is addressed by using a clear-field print pattern that is then coated with etch resist material. The printed clear field pattern is selectively removed to form an inverse pattern (darkfield) within the coated resist layer. Etching then removes selected portions of an underlying (e.g., encapsulation, conductive, etc.) layer. Removal of the mask produces a layer with large-area features with substantially reduced defects.
摘要翻译：当使用数字光刻技术时，由于喷射器脱落或滴落错误方向，暗场蚀刻掩模（大部分掩模区域不透明）对针孔缺陷，转印图案，不均匀性等的敏感性以及由于大面积覆盖而造成的长占空比（或印刷图案化）通过使用随后涂覆有抗蚀剂材料的透明场印刷图案来解决。选择性地去除打印的清晰场图案以在涂覆的抗蚀剂层内形成反向图案（暗场）。然后蚀刻去除底层（例如，封装，导电等）层的选定部分。去除掩模产生具有大面积特征并具有显着减少的缺陷的层。

7. 发明申请

US20070221610A1 Method using monolayer etch masks in combination with printed masks 失效
标题翻译：使用单层蚀刻掩模与印刷掩模组合的方法
公开(公告)号：US20070221610A1
公开(公告)日：2007-09-27
申请号：US11388718
申请日：2006-03-24
申请人： Eugene Chow , William Wong , Michael Chabinyc , Jeng Lu , Ana Arias
发明人： Eugene Chow , William Wong , Michael Chabinyc , Jeng Lu , Ana Arias
IPC分类号： H01B13/00 , B44C1/22
CPC分类号： H01L21/302 , H01L21/0271 , H01L21/0273 , H01L27/124 , H01L27/1288 , H01L27/1292 , H01L29/66765
摘要： A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.
摘要翻译：将薄膜图案尺寸小于印刷像素掩模尺寸的方法。印刷的掩模沉积在基底上的薄膜上。第二掩模层选择性地沉积在膜上，而不是印刷在掩模上。然后将第三掩模印刷到基底上以对第二掩模的一部分进行图案化。然后使用某些溶剂去除印刷的掩模，而不是薄膜上的掩模层。然后将掩模层与蚀刻结合在薄膜上形成图案。形成在薄膜中的特征小于印刷掩模的最小尺寸。涂覆的掩模层可以是选择性地结合薄膜的自组装单层或其它材料。

8. 发明申请

US20060131124A1 Self-forming microlenses for VCSEL arrays 有权
标题翻译： VCSEL阵列的自形成微透镜
公开(公告)号：US20060131124A1
公开(公告)日：2006-06-22
申请号：US11015937
申请日：2004-12-17
申请人： Michael Chabinyc , Patrick Maeda , Christopher Chua
发明人： Michael Chabinyc , Patrick Maeda , Christopher Chua
IPC分类号： F16D43/18
CPC分类号： B82Y30/00 , H01S5/0425 , H01S5/18388 , H01S5/423
摘要： A Vertical Cavity Surface Emitting Laser (VCSEL) assembly including a VCSEL structure having a light-emitting region located on its surface, a relatively wettable region of a surface modifier coating formed over the light emitting region, and a microlens formed on the relatively wettable region. A relatively non-wettable region of the surface modifier coating is formed around the light-emitting region (e.g., on the electrode surrounding the light-emitting region). The surface modifier coating is formed, for example, from one or more organothiols that change the surface energies of the light-emitting region and/or the electrode to facilitate self-assembly and self-registration of the microlens material. The microlens material is printed, microjetted, or dip coated onto the VCSEL structure such that the microlens material wets to the relatively wettable region, thereby forming a liquid bead that is reliably positioned over the light-emitting region. The liquid bead is then cured to form the microlens.
摘要翻译：包括具有位于其表面上的发光区域的VCSEL结构的垂直腔表面发射激光器（VCSEL）组件，形成在发光区域上的表面改性剂涂层的相对可润湿区域，以及形成在相对可润湿区域上的微透镜。在发光区域（例如，围绕发光区域的电极）周围形成表面改性剂涂层的相对不可润湿的区域。表面改性剂涂层例如由一种或多种改变发光区域和/或电极的表面能的有机硫醇形成，以促进微透镜材料的自组装和自配准。将微透镜材料印刷，微喷射或浸涂在VCSEL结构上，使得微透镜材料润湿到相对可润湿的区域，从而形成可靠地定位在发光区域上方的液体珠粒。然后将液体珠固化以形成微透镜。

9. 发明申请

US20050133788A1 ELECTRONIC DEVICE AND METHODS FOR FABRICATING AN ELECTRONIC DEVICE 失效
标题翻译：电子设备和用于制造电子设备的方法
公开(公告)号：US20050133788A1
公开(公告)日：2005-06-23
申请号：US10739189
申请日：2003-12-19
申请人： Michael Chabinyc , Alberto Salleo , William Wong
发明人： Michael Chabinyc , Alberto Salleo , William Wong
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L29/41 , H01L29/417 , H01L29/76 , H01L29/786 , H01L51/05 , H01L51/40
CPC分类号： H01L51/0545 , H01L29/41733 , H01L51/0021 , H01L51/057
摘要： An electronic device and a method of fabricating the electronic device includes forming a first electrical contact, a dielectric layer and a second electrical contact wherein the dielectric layer is located between the first and the second electrical contacts, forming an electrically insulating layer over the dielectric layer and the first electrical contact, exposing the first and second electrical contact, the dielectric layer and a first portion of the electrically insulating layer to radiation from the side of the first electrical contact, removing a second portion of the electrically insulating layer that was not irradiated by the radiation, providing a semiconductor material over a portion of the dielectric layer, and forming at least a third electrical contact over at least a portion of the electrically insulating layer and the semiconductor material.
摘要翻译：电子器件和制造该电子器件的方法包括形成第一电接触，电介质层和第二电接触，其中电介质层位于第一和第二电接触之间，在介电层上形成电绝缘层和所述第一电接触，使所述第一和第二电接触，所述电介质层和所述电绝缘层的第一部分暴露于从所述第一电接触侧的辐射，除去未被照射的所述电绝缘层的第二部分通过辐射，在电介质层的一部分上提供半导体材料，以及在电绝缘层和半导体材料的至少一部分上形成至少第三电接触。

10. 发明授权

US07749916B2 Additive printed mask process and structures produced thereby 有权
标题翻译：添加印刷掩模工艺和由此生产的结构
公开(公告)号：US07749916B2
公开(公告)日：2010-07-06
申请号：US12046242
申请日：2008-03-11
申请人： William Wong , Scott Limb , Michael Chabinyc , Beverly Russo , Rene Lujan
发明人： William Wong , Scott Limb , Michael Chabinyc , Beverly Russo , Rene Lujan
IPC分类号： H01L21/31
CPC分类号： G02F1/133512 , B41M3/003 , B41M3/006 , G02F1/133516 , G03F7/2018 , Y10S438/942
摘要： A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
摘要翻译：数字光刻工艺首先沉积由印刷图案掩模特征组成的掩模层。印刷图案掩模特征限定了可以沉积目标材料的间隙，优选通过数字光刻工艺。如果需要，目标材料被固化或硬化成目标特征。然后选择性地去除掩模层。剩余的目标特征然后可以用作曝光或蚀刻掩模，诸如流体容纳元件的物理结构等。可以在实现数字光刻的优点的同时获得精细特征宽度，更小的打印图案化掩模特征的最小宽度制造过程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式