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1. 发明申请

US20060284174A1 Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer 有权
标题翻译：用于在半导体晶片上并入的半导体芯片的测试装置
公开(公告)号：US20060284174A1
公开(公告)日：2006-12-21
申请号：US11477963
申请日：2006-06-28
申请人： Brion Keller , Bernd Koenemann , David Lackey , Donald Wheater
发明人： Brion Keller , Bernd Koenemann , David Lackey , Donald Wheater
IPC分类号： H01L23/58
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/2889 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits. The stimulus busses can also be used to provide each chip with parallel serial scan data as well as power and other signals such as clock and enable and disable signals. Each chip control circuit provides the chip with power, bus clock, control, enable and response lines, can also connected to each chip via suitable lines in the kerfs.
摘要翻译：将提供用于同时测试半导体晶片上的多个未切割芯片的多个通信路径的装置，其将同时允许每个这样的通信路径在使用最少数量的测试器接触的同时服务多于一个芯片。本发明的这些和其它目的，特征和优点在其上具有多个切口隔离的集成芯片的半导体晶片中实现，每个所述芯片通过两个不同的刺激总线耦合到策略放置的管理电路中的至少两个不同的管理电路 ; 每个芯片通过布置在芯片之间的切口区域中的选择控制电路耦合到每个管理电路。正是这种冗余可以显着降低相关管理或选择控制电路故障的可能性。刺激总线还可以用于为每个芯片提供并行串行扫描数据以及功率和其他信号，如时钟和使能和禁止信号。每个芯片控制电路为芯片提供电源，总线时钟，控制，使能和响应线路，还可以通过切口中的适当线路连接到每个芯片。

2. 发明授权

US06611933B1 Real-time decoder for scan test patterns 失效
标题翻译：扫描测试模式的实时解码器
公开(公告)号：US06611933B1
公开(公告)日：2003-08-26
申请号：US09547827
申请日：2000-04-12
申请人： Bernd Koenemann , Carl Barnhart , Brion Keller
发明人： Bernd Koenemann , Carl Barnhart , Brion Keller
IPC分类号： G01R3128
CPC分类号： G01R31/318547
摘要： A method and apparatus for improving the efficiency of scan testing of integrated circuits is described. This efficiency is achieved by reducing the amount of required test stimulus source data and by increasing the effective bandwidth of the scan-load operation. The reduced test data volume and corresponding test time are achieved by integrating a real-time test data decoder or logic network into each integrated circuit chip. The apparatus, servicing a plurality of internal scan chains wherein the number of said internal scan chains exceeds the number of primary inputs available for loading data into the scan chains, includes: a) logic network positioned between the primary inputs and the inputs of the scan chains, the logic network expanding input data words having a width corresponding to the number of the primary inputs, and converting the input data words into expanded output data words having a width that corresponds to the number of the internal scan chains; and b) coupled to the internal scan chains, registers loaded with bit values provided by the expanded output data words while data previously loaded into the scan chains shifts forward within the scan chains by one bit position at a time; wherein a first plurality of the input data words supplied to the primary inputs produce a second plurality of expanded data words that are loaded into the internal scan chains to achieve an improved test coverage.
摘要翻译：描述了一种提高集成电路扫描测试效率的方法和装置。该效率通过减少所需的测试刺激源数据量并通过增加扫描负载操作的有效带宽来实现。通过将实时测试数据解码器或逻辑网络集成到每个集成电路芯片中来实现降低的测试数据量和相应的测试时间。该装置服务于多个内部扫描链，其中所述内部扫描链的数量超过可用于将数据加载到扫描链中的主要输入的数量，包括：a）位于主要输入和扫描的输入之间的逻辑网络所述逻辑网络扩展具有与所述主要输入的数量对应的宽度的输入数据字，以及将所述输入数据字转换成具有与所述内部扫描链的数量相对应的宽度的扩展的输出数据字; 并且b）耦合到内部扫描链，加载由扩展的输出数据字提供的位值的寄存器，而预先加载到扫描链中的数据在扫描链中每次向前移动一位位置; 其中提供给主输入的第一多个输入数据字产生加载到内部扫描链中的第二多个扩展数据字，以实现改进的测试覆盖。

3. 发明授权

US07509551B2 Direct logic diagnostics with signature-based fault dictionaries 有权
标题翻译：直接逻辑诊断与基于签名的故障字典
公开(公告)号：US07509551B2
公开(公告)日：2009-03-24
申请号：US11497977
申请日：2006-08-01
申请人： Bernd Koenemann , Manish Sharma
发明人： Bernd Koenemann , Manish Sharma
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31703
摘要： Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.
摘要翻译：这里公开了用于在电路测试期间创建的签名执行诊断的方法，装置和系统的代表性实施例。例如，在本文公开的一个示例性方法中，接收由签名生成器生成的签名。在本实施例中，签名对应于电路对不超过一个测试图案的响应。将签名与故障字典的条目进行比较，如果条目标识了解释签名的故障，则故障字典的条目与签名相匹配，并且故障存储在故障候选列表中。

4. 发明申请

US20090177936A1 DIRECT LOGIC DIAGNOSTICS WITH SIGNATURE-BASED FAULT DICTIONARIES 有权
标题翻译：具有基于标识的故障字典的直接逻辑诊断
公开(公告)号：US20090177936A1
公开(公告)日：2009-07-09
申请号：US12404553
申请日：2009-03-16
申请人： Bernd Koenemann , Manish Sharma
发明人： Bernd Koenemann , Manish Sharma
IPC分类号： G01R31/3177 , G06F11/25 , G06F17/50
CPC分类号： G01R31/31703
摘要： Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.
摘要翻译：这里公开了用于在电路测试期间创建的签名执行诊断的方法，装置和系统的代表性实施例。例如，在本文公开的一个示例性方法中，接收由签名生成器生成的签名。在本实施例中，签名对应于电路对不超过一个测试图案的响应。将签名与故障字典的条目进行比较，如果条目标识了解释签名的故障，则故障字典的条目与签名相匹配，并且故障存储在故障候选列表中。

5. 发明申请

US20070038911A1 Direct logic diagnostics with signature-based fault dictionaries 有权
标题翻译：直接逻辑诊断与基于签名的故障字典
公开(公告)号：US20070038911A1
公开(公告)日：2007-02-15
申请号：US11497977
申请日：2006-08-01
申请人： Bernd Koenemann , Manish Sharma
发明人： Bernd Koenemann , Manish Sharma
IPC分类号： G01R31/28
CPC分类号： G01R31/31703
摘要： Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.
摘要翻译：这里公开了用于在电路测试期间创建的签名执行诊断的方法，装置和系统的代表性实施例。例如，在本文公开的一个示例性方法中，接收由签名生成器生成的签名。在本实施例中，签名对应于电路对不超过一个测试图案的响应。将签名与故障字典的条目进行比较，如果条目标识了解释签名的故障，则故障字典的条目与签名相匹配，并且故障存储在故障候选列表中。

6. 发明授权

US08166360B2 Direct logic diagnostics with signature-based fault dictionaries 有权
标题翻译：直接逻辑诊断与基于签名的故障字典
公开(公告)号：US08166360B2
公开(公告)日：2012-04-24
申请号：US12404553
申请日：2009-03-16
申请人： Bernd Koenemann , Manish Sharma
发明人： Bernd Koenemann , Manish Sharma
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31703
摘要： Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.
摘要翻译：这里公开了用于在电路测试期间创建的签名执行诊断的方法，装置和系统的代表性实施例。例如，在本文公开的一个示例性方法中，接收由签名生成器生成的签名。在本实施例中，签名对应于电路对不超过一个测试图案的响应。将签名与故障字典的条目进行比较，如果条目标识了解释签名的故障，则故障字典的条目与签名相匹配，并且故障存储在故障候选列表中。

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