专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06764949B2 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication 有权
公开(公告)号：US06764949B2
公开(公告)日：2004-07-20
申请号：US10334392
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2144
CPC分类号： H01L21/32139 , H01L21/0332
摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

2. 发明授权

US06764947B1 Method for reducing gate line deformation and reducing gate line widths in semiconductor devices 有权
标题翻译：减少半导体器件栅极线变形和减小栅极线宽度的方法
公开(公告)号：US06764947B1
公开(公告)日：2004-07-20
申请号：US10366801
申请日：2003-02-14
申请人： Darin Chan , Douglas J. Bonser , Marina V. Plat , Marilyn I. Wright , Chih Yuh Yang , Lu You , Scott A. Bell , Philip A. Fisher
发明人： Darin Chan , Douglas J. Bonser , Marina V. Plat , Marilyn I. Wright , Chih Yuh Yang , Lu You , Scott A. Bell , Philip A. Fisher
IPC分类号： H01L214763
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/32139
摘要： A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.
摘要翻译：在非晶碳硬掩模和待蚀刻的多晶硅层之间设置氧化硅应力释放部分以形成栅极线。应力消除部分减轻硬掩模和多晶硅之间的应力，从而降低在多晶硅图案化之前硬掩模的分层的风险。应力消除部分可以在图案化之前被修整，并且用作图案化多晶硅的蚀刻掩模。在图案化应力释放部分之前，可以修剪硬掩模的无定形碳以实现栅极线宽度的进一步降低。

3. 发明授权

US06773998B1 Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning 有权
标题翻译：改进的薄膜堆叠和图案化策略，用于应力补偿和防止无定形碳栅图案中的图案变形
公开(公告)号：US06773998B1
公开(公告)日：2004-08-10
申请号：US10445129
申请日：2003-05-20
申请人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
发明人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21336
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/31116 , H01L21/3146 , H01L21/32137 , H01L21/32139
摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.
摘要翻译：集成电路的方法包括使用无定形碳ARC掩模。一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

4. 发明授权

US06864556B1 CVD organic polymer film for advanced gate patterning 失效
标题翻译：用于先进栅极图案化的CVD有机聚合物膜
公开(公告)号：US06864556B1
公开(公告)日：2005-03-08
申请号：US10335445
申请日：2002-12-31
申请人： Lu You , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Richard J. Huang , Christopher F. Lyons , Mark S. Chang , Marilyn I. Wright
发明人： Lu You , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Richard J. Huang , Christopher F. Lyons , Mark S. Chang , Marilyn I. Wright
IPC分类号： G03F7/09 , H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/47 , H01L31/0232
CPC分类号： H01L21/32139 , G03F7/091 , H01L21/0332 , H01L21/28123 , H01L29/785
摘要： A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.
摘要翻译：采用底层抗反射涂层，其包含基本上不含氮的有机聚合物层和相对于多晶硅层的低压缩应力作为双层抗反射涂层/硬掩模结构的下层，以减少图案的变形形成在可图案层中。有机聚合物层对可见辐射基本上是透明的，能够在半导体器件制造过程中更好地检测对准标记并提高覆盖精度。有机聚合物层提供优异的台阶覆盖，并且可以有利地用于制造诸如FinFET的结构。

5. 发明授权

US06750127B1 Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance 有权
标题翻译：使用具有改善的耐蚀性的非晶碳制造半导体器件的方法
公开(公告)号：US06750127B1
公开(公告)日：2004-06-15
申请号：US10367407
申请日：2003-02-14
申请人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
发明人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
IPC分类号： H01L213205
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337
摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.
摘要翻译：注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

6. 发明授权

US06900002B1 Antireflective bi-layer hardmask including a densified amorphous carbon layer 有权
标题翻译：包括致密非晶碳层的抗反射双层硬掩模
公开(公告)号：US06900002B1
公开(公告)日：2005-05-31
申请号：US10299427
申请日：2002-11-19
申请人： Marina V. Plat , Marilyn I. Wright , Lu You , Scott A. Bell
发明人： Marina V. Plat , Marilyn I. Wright , Lu You , Scott A. Bell
IPC分类号： G03F7/00 , G03F7/09 , H01L21/027 , H01L21/3105 , H01L21/3213
CPC分类号： H01L21/32139 , G03F7/091 , H01L21/0276 , H01L21/31058
摘要： An amorphous carbon layer of an antireflective bi-layer hardmask is processed to increase its density prior to patterning of an underlying polysilicon layer using the bi-layer hardmask. The increased density of the layer increases its resistance to polysilicon etch chemistry, thus reducing the likelihood of patterning inaccuracies resulting from amorphous carbon depletion during polysilicon etch, and enabling the patterning of thicker polysilicon layers than can be reliably patterned without densification. The increased density also reduces stresses, thus reducing the likelihood of delamination. Densification may be performed by UV or e-beam irradiation after formation of an overlying protective layer. Densification may also be performed by annealing the amorphous carbon layer in situ prior to formation of the overlying protective layer. In the latter case, annealing reduces the amount of outgassing that occurs during formation of the protective layer, thus reducing the formation of pin holes.
摘要翻译：在使用双层硬掩模对下面的多晶硅层进行图案化之前，处理抗反射双层硬掩模的无定形碳层以增加其密度。层的增加的密度增加了其对多晶硅蚀刻化学性质的抵抗力，从而降低了在多晶硅蚀刻期间由无定形碳耗尽导致的不准确图案的可能性，并且使得能够在不致密化的情况下可靠地图案化更厚的多晶硅层的图案化。增加的密度也降低了应力，从而降低了分层的可能性。在形成上覆保护层之后，可以通过UV或电子束照射进行致密化。还可以通过在形成上覆保护层之前将非晶碳层原位退火来进行致密化。在后一种情况下，退火减少了在形成保护层期间发生的除气量，从而减少了针孔的形成。

7. 发明授权

US06893967B1 L-shaped spacer incorporating or patterned using amorphous carbon or CVD organic materials 有权
标题翻译：使用无定形碳或CVD有机材料结合或图案化的L形间隔物
公开(公告)号：US06893967B1
公开(公告)日：2005-05-17
申请号：US10755911
申请日：2004-01-13
申请人： Marilyn I. Wright , Douglas J. Bonser , Lu You , Kay Hellig
发明人： Marilyn I. Wright , Douglas J. Bonser , Lu You , Kay Hellig
IPC分类号： H01L29/72
CPC分类号： H01L29/6656
摘要： A multilayer L-shaped spacer is formed of a lower portion comprising a CVD organic material or amorphous carbon, and an upper portion comprised of a protective material. The upper portion is patterned using a photoresist mask. During that patterning, the underlying substrate is protected by a layer of CVD organic material or amorphous carbon. The CVD organic material or amorphous carbon is then patterned using the patterned protective material as a mask. The chemistry used to pattern the CVD organic material or amorphous carbon is relatively harmless to the underlying substrate. Alternatively, an L-shaped spacer is patterned without using a photoresist mask by forming an amorphous carbon spacer around a gate that is covered with a conformal layer of a conventional spacer material. The conventional spacer material is patterned using the amorphous carbon spacer as an etch mask. The amorphous carbon spacer is easily formed without the need for lithographic patterning, and therefore this method is preferable to methods using photoresist masks.
摘要翻译：多层L型间隔件由包含CVD有机材料或无定形碳的下部和由保护材料构成的上部形成。使用光致抗蚀剂掩模对上部进行图案化。在该图案化期间，下面的衬底被CVD有机材料层或无定形碳保护。然后使用图案化的保护材料作为掩模对CVD有机材料或无定形碳进行图案化。用于对CVD有机材料或无定形碳进行图案化学的化学物质对于底层基材相对无害。或者，通过在被常规间隔物材料的共形层覆盖的栅极周围形成无定形碳隔离物，将L形间隔物图案化而不使用光致抗蚀剂掩模。使用无定形碳间隔物作为蚀刻掩模来对传统的间隔物材料进行图案化。非晶碳隔离物容易地形成而不需要平版印刷图案，因此该方法优于使用光致抗蚀剂掩模的方法。

8. 发明授权

US08629535B2 Mask for forming integrated circuit 有权
标题翻译：用于形成集成电路的掩模
公开(公告)号：US08629535B2
公开(公告)日：2014-01-14
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L23/58
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

9. 发明申请

US20120007221A1 MASK FOR FORMING INTEGRATED CIRCUIT 有权
标题翻译：形成集成电路的掩模
公开(公告)号：US20120007221A1
公开(公告)日：2012-01-12
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L29/66 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

10. 发明授权

US07521304B1 Method for forming integrated circuit 失效
标题翻译：集成电路形成方法
公开(公告)号：US07521304B1
公开(公告)日：2009-04-21
申请号：US10230775
申请日：2002-08-29
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式