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1. 发明申请

US20100048043A1 Matched-Impedance Connector Footprints 有权
公开(公告)号：US20100048043A1
公开(公告)日：2010-02-25
申请号：US12604529
申请日：2009-10-23
申请人： Danny L.C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
发明人： Danny L.C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
IPC分类号： H01R12/04
CPC分类号： H05K1/114 , H05K1/0219 , H05K1/0237 , H05K2201/09227 , H05K2201/09236 , H05K2201/10189 , H05K2201/10734
摘要： Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.

2. 发明申请

US20100041275A1 Matched-Impedance Connector Footprints 有权
公开(公告)号：US20100041275A1
公开(公告)日：2010-02-18
申请号：US12604465
申请日：2009-10-23
申请人： Danny L.C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
发明人： Danny L.C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
IPC分类号： H01R13/648
CPC分类号： H05K1/114 , H05K1/0219 , H05K1/0237 , H05K2201/09227 , H05K2201/09236 , H05K2201/10189 , H05K2201/10734
摘要： Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.

3. 发明申请

US20100041256A1 Matched-Impedance Connector Footprints 有权
标题翻译：匹配阻抗连接器脚印
公开(公告)号：US20100041256A1
公开(公告)日：2010-02-18
申请号：US12604459
申请日：2009-10-23
申请人： Danny L.C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
发明人： Danny L.C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
IPC分类号： H01R13/648
CPC分类号： H05K1/114 , H05K1/0219 , H05K1/0237 , H05K2201/09227 , H05K2201/09236 , H05K2201/10189 , H05K2201/10734
摘要： Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.
摘要翻译：公开了用于在诸如印刷电路板的基板上定义匹配阻抗覆盖区的方法，例如适于接收具有端子引线布置的电气部件。这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。通孔布置可以不同于衬垫布置。通孔可以被布置成增加布线密度，同时限制串扰并且提供组件和基板之间的匹配阻抗。可以改变通孔布置以在板的层上实现期望的布线密度。增加布线密度可能会减少电路板层数，这往往会降低电容，从而增加阻抗。接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。因此，可以改变通孔布置以实现与部件的阻抗匹配的阻抗。也可以改变通孔装置以限制相邻信号导体之间的串扰。因此，可以定义通孔布置以平衡系统的阻抗，串扰和布线密度要求。

4. 发明授权

US08383951B2 Matched-impedance connector footprints 有权
标题翻译：匹配阻抗连接器脚印
公开(公告)号：US08383951B2
公开(公告)日：2013-02-26
申请号：US12604465
申请日：2009-10-23
申请人： Danny L. C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
发明人： Danny L. C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
IPC分类号： H05K1/11
CPC分类号： H05K1/114 , H05K1/0219 , H05K1/0237 , H05K2201/09227 , H05K2201/09236 , H05K2201/10189 , H05K2201/10734
摘要： Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.
摘要翻译：公开了用于在诸如印刷电路板的基板上定义匹配阻抗覆盖区的方法，例如适于接收具有端子引线布置的电气部件。这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。通孔布置可以不同于衬垫布置。通孔可以被布置成增加布线密度，同时限制串扰并且提供组件和基板之间的匹配阻抗。可以改变通孔布置以在板的层上实现期望的布线密度。增加布线密度可能会减少电路板层数，这往往会降低电容，从而增加阻抗。接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。因此，可以改变通孔布置以实现与部件的阻抗匹配的阻抗。也可以改变通孔装置以限制相邻信号导体之间的串扰。因此，可以定义通孔布置以平衡系统的阻抗，串扰和布线密度要求。

5. 发明授权

US08183466B2 Matched-impedance connector footprints 有权
标题翻译：匹配阻抗连接器脚印
公开(公告)号：US08183466B2
公开(公告)日：2012-05-22
申请号：US12604529
申请日：2009-10-23
申请人： Danny L. C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
发明人： Danny L. C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
IPC分类号： H05K1/11
CPC分类号： H05K1/114 , H05K1/0219 , H05K1/0237 , H05K2201/09227 , H05K2201/09236 , H05K2201/10189 , H05K2201/10734
摘要： Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.
摘要翻译：公开了用于在诸如印刷电路板的基板上定义匹配阻抗覆盖区的方法，例如适于接收具有端子引线布置的电气部件。这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。通孔布置可以不同于衬垫布置。通孔可以被布置成增加布线密度，同时限制串扰并且提供组件和基板之间的匹配阻抗。可以改变通孔布置以在板的层上实现期望的布线密度。增加布线密度可能会减少电路板层数，这往往会降低电容，从而增加阻抗。接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。因此，可以改变通孔布置以实现与部件的阻抗匹配的阻抗。也可以改变通孔装置以限制相邻信号导体之间的串扰。因此，可以定义通孔布置以平衡系统的阻抗，串扰和布线密度要求。

6. 发明授权

US07935896B2 Matched-impedance connector footprints 有权
标题翻译：匹配阻抗连接器脚印
公开(公告)号：US07935896B2
公开(公告)日：2011-05-03
申请号：US12604459
申请日：2009-10-23
申请人： Danny L. C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
发明人： Danny L. C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan DeGeest
IPC分类号： H05K1/11
CPC分类号： H05K1/114 , H05K1/0219 , H05K1/0237 , H05K2201/09227 , H05K2201/09236 , H05K2201/10189 , H05K2201/10734
摘要： Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.
摘要翻译：公开了用于在诸如印刷电路板的基板上定义匹配阻抗覆盖区的方法，例如适于接收具有端子引线布置的电气部件。这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。通孔布置可以不同于衬垫布置。通孔可以被布置成增加布线密度，同时限制串扰并且提供组件和基板之间的匹配阻抗。可以改变通孔布置以在板的层上实现期望的布线密度。增加布线密度可能会减少电路板层数，这往往会降低电容，从而增加阻抗。接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。因此，可以改变通孔布置以实现与部件的阻抗匹配的阻抗。也可以改变通孔装置以限制相邻信号导体之间的串扰。因此，可以定义通孔布置以平衡系统的阻抗，串扰和布线密度要求。

7. 发明授权

US07709747B2 Matched-impedance surface-mount technology footprints 有权
标题翻译：匹配阻抗表面贴装技术的脚印
公开(公告)号：US07709747B2
公开(公告)日：2010-05-04
申请号：US11287926
申请日：2005-11-28
申请人： Danny L. C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan De Geest
发明人： Danny L. C. Morlion , Stefaan Sercu , Winnie Heyvaert , Jan De Geest
IPC分类号： H01R12/04 , H05K1/11
CPC分类号： H05K1/114 , H05K1/0219 , H05K1/0237 , H05K2201/09227 , H05K2201/09236 , H05K2201/10189 , H05K2201/10734
摘要： Disclosed are methodologies for defining matched-impedance surface-mount technology footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.
摘要翻译：公开了用于在诸如印刷电路板的基板上定义匹配阻抗表面贴装技术足迹的方法，例如适于接收具有端子引线布置的电气部件。这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。通孔布置可以不同于衬垫布置。通孔可以被布置成增加布线密度，同时限制串扰并且提供组件和基板之间的匹配阻抗。可以改变通孔布置以在板的层上实现期望的布线密度。增加布线密度可能会减少电路板层数，这往往会降低电容，从而增加阻抗。接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。因此，可以改变通孔布置以实现与部件的阻抗匹配的阻抗。也可以改变通孔装置以限制相邻信号导体之间的串扰。因此，可以定义通孔布置以平衡系统的阻抗，串扰和布线密度要求。

8. 发明申请

US20060232301A1 Matched-impedance surface-mount technology footprints 有权
标题翻译：匹配阻抗表面贴装技术的脚印
公开(公告)号：US20060232301A1
公开(公告)日：2006-10-19
申请号：US11287926
申请日：2005-11-28
申请人： Danny Morlion , Stefaan Sercu , Winnie Heyvaert , Jan De Geest
发明人： Danny Morlion , Stefaan Sercu , Winnie Heyvaert , Jan De Geest
IPC分类号： H03K19/086 , H03K19/20
CPC分类号： H05K1/114 , H05K1/0219 , H05K1/0237 , H05K2201/09227 , H05K2201/09236 , H05K2201/10189 , H05K2201/10734
摘要： Disclosed are methodologies for defining matched-impedance surface-mount technology footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.
摘要翻译：公开了用于在诸如印刷电路板的基板上定义匹配阻抗表面贴装技术足迹的方法，例如适于接收具有端子引线布置的电气部件。这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。通孔布置可以不同于衬垫布置。通孔可以被布置成增加布线密度，同时限制串扰并且提供组件和基板之间的匹配阻抗。可以改变通孔布置以在板的层上实现期望的布线密度。增加布线密度可能会减少电路板层数，这往往会降低电容，从而增加阻抗。接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。因此，可以改变通孔布置以实现与部件的阻抗匹配的阻抗。也可以改变通孔装置以限制相邻信号导体之间的串扰。因此，可以定义通孔布置以平衡系统的阻抗，串扰和布线密度要求。

9. 发明申请

US20070099464A1 Shieldless, High-Speed Electrical Connectors 有权
标题翻译：无屏蔽，高速电气连接器
公开(公告)号：US20070099464A1
公开(公告)日：2007-05-03
申请号：US11610678
申请日：2006-12-14
申请人： Clifford Winings , Joseph Shuey , Timothy Lemke , Stephen Smith , Stefaan Sercu
发明人： Clifford Winings , Joseph Shuey , Timothy Lemke , Stephen Smith , Stefaan Sercu
IPC分类号： H01R13/62
CPC分类号： H01R12/52 , H01R12/724 , H01R13/6471 , H01R13/6477 , H01R13/6587 , H01R29/00 , Y10S439/941
摘要： An electrical connector having a leadframe housing, a first electrical contact fixed in the leadframe housing, a second electrical contact fixed adjacent to the first electrical contact in the leadframe housing, and a third electrical contact fixed adjacent to the second electrical contact in the leadframe housing is disclosed. Each of the first and second electrical contacts may be selectively designated, while fixed in the lead frame housing, as either a ground contact or a signal contact such that, in a first designation, the first and second contacts form a differential signal pair, and, in a second designation, the second contact is a single-ended signal conductor. The third electrical contact may be a ground contact having a terminal end that extends beyond terminal ends of the first and second contacts.
摘要翻译：一种电连接器，具有引线框架壳体，固定在引线框架壳体中的第一电触点，与引线框架壳体中的第一电触头相邻固定的第二电触头，以及与引线框壳体中的第二电触头相邻固定的第三电触点被披露。第一和第二电触头中的每个可以被选择性地指定为固定在引线框架壳体中，作为接地触点或信号触点，使得在第一指定中，第一和第二触点形成差分信号对，以及在第二指定中，第二触点是单端信号导体。第三电触点可以是具有延伸超过第一和第二触点的终端的终端的接地触头。

10. 发明申请

US20060234532A1 Shieldless, high-speed electrical connectors 有权
标题翻译：无屏蔽，高速电气连接器
公开(公告)号：US20060234532A1
公开(公告)日：2006-10-19
申请号：US11326175
申请日：2006-01-05
申请人： Clifford Winings , Joseph Shuey , Timothy Lemke , Gregory Hull , Stephen Smith , Stefaan Sercu , Timothy Houtz , Steven Minich
发明人： Clifford Winings , Joseph Shuey , Timothy Lemke , Gregory Hull , Stephen Smith , Stefaan Sercu , Timothy Houtz , Steven Minich
IPC分类号： H01R13/648
CPC分类号： H01R12/52 , H01R12/724 , H01R13/6471 , H01R13/6477 , H01R13/6587 , H01R29/00 , Y10S439/941
摘要： An electrical connector that includes a linear array of electrical blade contacts is disclosed. Each contact may have a free-ended mating portion that extends from a mate surface of a dielectric base. The first linear array may include a first signal contact, a second signal contact positioned adjacent to the first signal contact and forming a differential signal pair therewith, and a ground contact positioned adjacent to the second signal contact. The first signal contact, the second signal contact, and the ground contact may each be elongated in a direction along the linear array.
摘要翻译：公开了一种包括电子叶片触点的线性阵列的电连接器。每个接触件可以具有从电介质基底的配合表面延伸的自由端配合部分。第一线性阵列可以包括第一信号触点，邻近第一信号触点定位的第二信号触点，并与其形成差分信号对，以及定位成与第二信号触点相邻的接地触点。第一信号触点，第二信号触点和接地触头可以沿着线性阵列的方向各自伸长。

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