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1. 发明授权

US5886920A Variable conducting element and method of programming 失效
标题翻译：可变导体元件及编程方法
公开(公告)号：US5886920A
公开(公告)日：1999-03-23
申请号：US982175
申请日：1997-12-01
申请人： Daniel S. Marshall , Jerald Allen Hallmark , David J. Anderson , Ellen Lan
发明人： Daniel S. Marshall , Jerald Allen Hallmark , David J. Anderson , Ellen Lan
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22 , G11C11/223
摘要： A variable conducting element (10) and method for programming a constant current or constant resistance provided at output terminals (24 and 26) of a ferroelectric transistor (12). The ferroelectric transistor (12) has portions of a ferroelectric material (32A) programmed having up-polarization states separated by domain walls (34) from portions of a ferroelectric material (32B) programmed having down-polarization states. The portion of the ferroelectric material (32A) programmed in the up-polarization state forms current conduction channels between a source region (23) and a drain region (25) of the ferroelectric transistor (12). The ferroelectric transistor (12) is programmed through a capacitor (14) to adjust the charge supplied to a control terminal (22) of the ferroelectric transistor (12).
摘要翻译：一种用于编程在铁电晶体管（12）的输出端（24和26）处提供的恒定电流或恒定电阻的可变导体元件（10）和方法。铁电晶体管（12）具有编程具有由畴壁（34）与被编程为具有向下极化状态的铁电材料（32B）的部分分离的上极化状态的铁电材料（32A）的部分。以上极化状态编程的铁电材料（32A）的部分在铁电晶体管（12）的源极区（23）和漏极区（25）之间形成电流传导沟道。铁电晶体管（12）通过电容器（14）编程，以调节提供给铁电晶体管（12）的控制端子（22）的电荷。

2. 发明授权

US06262451B1 Electrode structure for transistors, non-volatile memories and the like 失效
标题翻译：晶体管的电极结构，非易失性存储器等
公开(公告)号：US06262451B1
公开(公告)日：2001-07-17
申请号：US08816707
申请日：1997-03-13
申请人： Jenn-Hwa Huang , Kurt Eisenbeiser , Yang Wang , Ellen Lan
发明人： Jenn-Hwa Huang , Kurt Eisenbeiser , Yang Wang , Ellen Lan
IPC分类号： H01L29788
CPC分类号： H01L29/4983 , H01L21/2815 , H01L29/41775 , H01L29/41783 , H01L29/66325 , H01L29/66484 , H01L29/6656 , H01L29/66575 , H01L29/66825 , H01L29/7831 , H01L29/7832 , H01L29/792 , H01L29/8124 , Y10S257/90
摘要： An electrode structure for semiconductor devices includes first electrode material positioned in overlying relationship to the surface of a substrate so as to define a first side wall perpendicular thereto. A nonconductive side wall spacer is formed on the first side wall and defines a second side wall parallel to and spaced from the first side wall. Second electrode material is formed in overlying relationship to the substrate and on the second side wall so as to define a third side wall parallel to and spaced from the second side wall. The first and second electrode materials are connected as first and second electrodes in a common semiconductor device. Additional electrodes can be formed by forming electrode material on additional side walls.
摘要翻译：用于半导体器件的电极结构包括以与衬底的表面相重叠的方式定位的第一电极材料，以便限定与其垂直的第一侧壁。在第一侧壁上形成非导电侧壁隔离件并且限定平行于第一侧壁并与第一侧壁间隔开的第二侧壁。第二电极材料以与衬底和第二侧壁重叠的关系形成，以便限定与第二侧壁平行并与第二侧壁间隔开的第三侧壁。第一和第二电极材料在公共半导体器件中作为第一和第二电极连接。可以通过在另外的侧壁上形成电极材料来形成附加的电极。

3. 发明申请

US20060043416A1 Recessed semiconductor device 有权
标题翻译：嵌入式半导体器件
公开(公告)号：US20060043416A1
公开(公告)日：2006-03-02
申请号：US10925855
申请日：2004-08-25
申请人： Hsin-Hua P. Li , Bruce Green , Olin Hartin , Ellen Lan , Charles Weitzel
发明人： Hsin-Hua P. Li , Bruce Green , Olin Hartin , Ellen Lan , Charles Weitzel
IPC分类号： H01L31/0328
CPC分类号： H01L29/7785 , H01L21/28593 , H01L29/2003 , H01L29/66462
摘要： A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.
摘要翻译：半导体结构包括第一半导体层，第一半导体层上的第二半导体层，第二半导体层上的第三半导体层以及第三半导体层上的第四半导体层。第一导电部分耦合到第一半导体层，并且在第一半导体层上形成第二导电部分。

4. 发明授权

US06156611A Method of fabricating vertical FET with sidewall gate electrode 失效
标题翻译：制造具有侧壁栅电极的垂直FET的方法
公开(公告)号：US06156611A
公开(公告)日：2000-12-05
申请号：US119550
申请日：1998-07-20
申请人： Ellen Lan , Jenn-Hwa Huang , Kurt Eisenbeiser , Yang Wang
发明人： Ellen Lan , Jenn-Hwa Huang , Kurt Eisenbeiser , Yang Wang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66522 , H01L29/7827
摘要： A vertical FET is fabricated by etching through a contact layer into a drift layer on a compound semiconductor substrate to form a plurality of mesas, each mesa having an upper surface and each adjacent pair of mesas defining therebetween a trench with sidewalls and a bottom. A conductive layer is conformally deposited over the plurality of mesas and the trenches and anisotropically etched to form contacts on the sidewalls of the trenches and depositing source contacts on the upper surfaces of the mesas and a drain contact on a reverse side of the substrate.
摘要翻译：通过将接触层蚀刻到化合物半导体衬底上的漂移层中以形成多个台面来制造垂直FET，每个台面具有上表面，并且每个相邻的一对台面在其间限定具有侧壁和底部的沟槽。导电层被共形沉积在多个台面和沟槽上并且各向异性地蚀刻以在沟槽的侧壁上形成接触，并且将沉积源触点放置在台面的上表面上以及在衬底的背面上的漏极接触。

5. 发明授权

US06939781B2 Method of manufacturing a semiconductor component that includes self-aligning a gate electrode to a field plate 失效
标题翻译：制造半导体部件的方法，其包括将栅电极自对准到场板
公开(公告)号：US06939781B2
公开(公告)日：2005-09-06
申请号：US10609106
申请日：2003-06-27
申请人： Randy D. Redd , Paul A. Fisher , Olin L. Hartin , Lawrence S. Klingbeil , Ellen Lan , Hsin-Hua P. Li , Charles E. Weitzel
发明人： Randy D. Redd , Paul A. Fisher , Olin L. Hartin , Lawrence S. Klingbeil , Ellen Lan , Hsin-Hua P. Li , Charles E. Weitzel
IPC分类号： H01L21/338 , H01L29/812 , H01L21/76
CPC分类号： H01L29/66871 , H01L29/402 , H01L29/42316 , H01L29/812
摘要： In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (110), a first dielectric layer (120) above the semiconductor substrate, a first ohmic contact region (410) and a second ohmic contact region (420) above the semiconductor substrate, a gate electrode (1120) above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate (210) above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer (310) above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer (910) between the gate electrode and the field plate and not located above the gate electrode or the field plate.
摘要翻译：在本发明的一个实施例中，半导体部件包括半导体衬底（110），半导体衬底上方的第一介电层（120），半导体上方的第一欧姆接触区（410）和第二欧姆接触区（420）衬底，半导体衬底之上和第一欧姆接触区域和第二欧姆接触区域之间的栅极电极（1120），在第一介电层上方以及栅电极和第二欧姆接触区域之间的场板（210），位于场板上方的第二电介质层（310），第一电介质层，第一欧姆接触区域和第二欧姆接触区域，以及栅电极和场板之间的第三介电层（910）栅电极或场板。

6. 发明授权

US6091621A Non-volatile multistate memory cell using a ferroelectric gate fet 失效
标题翻译：使用铁电栅极的非易失性多态存储单元
公开(公告)号：US6091621A
公开(公告)日：2000-07-18
申请号：US985456
申请日：1997-12-05
申请人： Yang Wang , Jenn-Hwa Huang , Kurt Eisenbeiser , Ellen Lan , William J. Ooms
发明人： Yang Wang , Jenn-Hwa Huang , Kurt Eisenbeiser , Ellen Lan , William J. Ooms
IPC分类号： G11C11/22 , G11C11/56
CPC分类号： G11C11/22 , G11C11/5657
摘要： A multi-state non-volatile ferroelectric memory includes a field effect transistor having a gate insulator formed of ferroelectric material. The ferroelectric material is separated into regions of different characteristics, e.g. different thicknesses, different coercive field values, etc., so as to provide a plurality of different threshold voltages for the field effect transistor.
摘要翻译：多状态非易失性铁电存储器包括具有由铁电材料形成的栅极绝缘体的场效应晶体管。铁电材料被分成不同特性的区域，例如不同的厚度，不同的矫顽场值等，以便为场效应晶体管提供多个不同的阈值电压。

7. 发明授权

US07253486B2 Field plate transistor with reduced field plate resistance 有权
标题翻译：场板电阻降低的场板晶体管
公开(公告)号：US07253486B2
公开(公告)日：2007-08-07
申请号：US10209746
申请日：2002-07-31
申请人： Bruce M. Green , Ellen Lan , Phillip Li
发明人： Bruce M. Green , Ellen Lan , Phillip Li
IPC分类号： H01L29/76
CPC分类号： H01L29/405 , H01L29/812
摘要： In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The field plate (40) comprises a plurality of connection locations (47) and a plurality of electrical connectors (45) connecting said plurality of connection locations (47) to a potential.
摘要翻译：在一个示例性实施例中，提供了晶体管（100）。晶体管（100）包括源（10），栅极（30），漏极（20）和位于栅极（30）和漏极（20）之间的场板（40）。场板（40）包括将所述多个连接位置（47）连接到电位的多个连接位置（47）和多个电连接器（45）。

8. 发明申请

US20060220062A1 pHEMT with barrier optimized for low temperature operation 有权
标题翻译： pHEMT具有针对低温操作优化的阻挡层
公开(公告)号：US20060220062A1
公开(公告)日：2006-10-05
申请号：US11100095
申请日：2005-04-05
申请人： Bruce Green , Olin Hartin , Ellen Lan , Philip Li , Monte Miller , Matthias Passlack , Marcus Ray , Charles Weitzel
发明人： Bruce Green , Olin Hartin , Ellen Lan , Philip Li , Monte Miller , Matthias Passlack , Marcus Ray , Charles Weitzel
IPC分类号： H01L29/739
CPC分类号： H01L29/7785
摘要： In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1-xAs layer (506) is formed over the buffer layer (504) and has a first doped region (508) formed therein. An InxGa1-xAs channel layer (512) is formed over the AlxGa1-xAs layer (506). An AlxGa1-xAs layer (518) is formed over the InxGa1-xAs channel layer (512), and the AlxGa1-xAs layer (518) has a second doped region formed therein. A GaAs layer (520) having a first recess is formed over the AlxGa1-xAs layer (518). A control electrode (526) is formed over the AlxGa1-xAs layer (518). A doped GaAs layer (524) is formed over the undoped GaAs layer (520) and on opposite sides of the control electrode (526) and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device (500) maintains linear operation over a wide temperature range.
摘要翻译：在一个实施例中，半导体器件（500）包括形成在衬底（502）上的缓冲层（504）。在缓冲层（504）之上形成Al x Ga 1-x As层（506），并且在其中形成有第一掺杂区域（508）。在Al x Ga 1-x 上形成一个In 1 / x Ga 1-x As As沟道层（512） >作为层（506）。在In 1 x 1 Ga 1-x N上形成Al x Ga 1-x As层（518）作为沟道层（512）和Al x Ga 1-x As层（518）具有形成在其中的第二掺杂区域。具有第一凹陷的GaAs层（520）形成在Al 1 Ga 1-x As层（518）上。控制电极（526）形成在Al 1 Ga 1-x As As层（518）上。在未掺杂的GaAs层（520）上和控制电极（526）的相对侧上形成掺杂GaAs层（524），并提供第一和第二电流电极。当用于放大数字调制信号时，半导体器件（500）在宽的温度范围内保持线性操作。

9. 发明申请

US20050104087A1 InGaP pHEMT device for power amplifier operation over wide temperature range 审中-公开
标题翻译： InGaP pHEMT器件用于宽温度范围内的功率放大器工作
公开(公告)号：US20050104087A1
公开(公告)日：2005-05-19
申请号：US10881162
申请日：2004-06-30
申请人： Ellen Lan , Monica De Baca , Bruce Green , Monte Miller , Charles Weitzel
发明人： Ellen Lan , Monica De Baca , Bruce Green , Monte Miller , Charles Weitzel
IPC分类号： H01L29/778 , H03F1/30 , H01L31/0328 , H01L29/739
CPC分类号： H03F1/301 , H01L29/7785
摘要： In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1-xAs layer (506) is formed over the buffer layer (504) and has a first doped region (508) formed therein. An InxGa1-xAs channel layer (512) is formed over the AlxGa1-xAs layer (506). An InxGa1-xP barrier layer (518) is formed over the InxGa1-xAs channel layer (512), the InxGa1-xP layer (518) has a second doped region formed therein. A control electrode (526) is formed over the InxGa1-xP layer (518). An undoped GaAs layer (520) is formed over the InxGa1-xP layer (518) adjacent to the control electrode (526). A doped GaAs layer (524) is formed over the undoped GaAs layer (520) and on opposite sides of the control electrode (526) and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device (500) maintains linear operation over a wide temperature range.
摘要翻译：在一个实施例中，半导体器件（500）包括形成在衬底（502）上的缓冲层（504）。在缓冲层（504）之上形成Al x Ga 1-x As层（506），并且在其中形成有第一掺杂区域（508）。在Al x Ga 1-x 上形成一个In 1 / x Ga 1-x As As沟道层（512） >作为层（506）。在In 1 / x Ga 1-x 作为沟道层（512），In 1 / x Ga 1-x P层（518）具有形成在其中的第二掺杂区域。控制电极（526）形成在In 1 x 1 Ga 1-x P层（518）上。在与控制电极（526）相邻的In 1 x 1 Ga 1-x P P层（518）上形成未掺杂的GaAs层（520）。在未掺杂的GaAs层（520）上和控制电极（526）的相对侧上形成掺杂GaAs层（524），并提供第一和第二电流电极。当用于放大数字调制信号时，半导体器件（500）在宽的温度范围内保持线性操作。

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