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1. 发明授权

US07710144B2 Controlling for variable impedance and voltage in a memory system 有权
标题翻译：控制存储系统中的可变阻抗和电压
公开(公告)号：US07710144B2
公开(公告)日：2010-05-04
申请号：US12165804
申请日：2008-07-01
申请人： Daniel M. Dreps , David J. Chen , William F. Lawson , David W. Mann
发明人： Daniel M. Dreps , David J. Chen , William F. Lawson , David W. Mann
IPC分类号： H03K17/16 , G06F17/50
CPC分类号： G06F13/4072 , G06F13/4086
摘要： A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.
摘要翻译：提供了一种用于控制存储器系统中的可变阻抗和电压的存储器接口设备，系统，方法和设计结构。存储器接口装置包括可配置为相对于外部参考电阻器调整输出阻抗的校准单元，以及包括耦合到存储器系统中的驱动器输出的多个正驱动电路和多个负驱动电路的驱动器电路。存储器接口装置还包括阻抗控制逻辑，用于调整校准单元的输出阻抗，并且选择性地使正和负驱动电路作为驱动电压和目标阻抗的函数。

2. 发明申请

US20100001758A1 CONTROLLING FOR VARIABLE IMPEDANCE AND VOLTAGE IN A MEMORY SYSTEM 有权
标题翻译：控制存储系统中的可变阻抗和电压
公开(公告)号：US20100001758A1
公开(公告)日：2010-01-07
申请号：US12165804
申请日：2008-07-01
申请人： Daniel M. Dreps , David J. Chen , William F. Lawson , David W. Mann
发明人： Daniel M. Dreps , David J. Chen , William F. Lawson , David W. Mann
IPC分类号： H03K17/16 , G11C8/00 , H03K19/0175
CPC分类号： G06F13/4072 , G06F13/4086
摘要： A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.
摘要翻译：提供了一种用于控制存储器系统中的可变阻抗和电压的存储器接口设备，系统，方法和设计结构。存储器接口装置包括可配置为相对于外部参考电阻器调整输出阻抗的校准单元，以及包括耦合到存储器系统中的驱动器输出的多个正驱动电路和多个负驱动电路的驱动器电路。存储器接口装置还包括阻抗控制逻辑，用于调整校准单元的输出阻抗，并且选择性地使正和负驱动电路作为驱动电压和目标阻抗的函数。

3. 发明授权

US08284621B2 Strobe offset in bidirectional memory strobe configurations 有权
标题翻译：双向内存选通配置中的频闪偏移
公开(公告)号：US08284621B2
公开(公告)日：2012-10-09
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C8/18
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译：一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

4. 发明申请

US20110199843A1 Strobe Offset in Bidirectional Memory Strobe Configurations 有权
标题翻译：双向内存频闪配置中的频闪偏移
公开(公告)号：US20110199843A1
公开(公告)日：2011-08-18
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译：一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

5. 发明授权

US08493801B2 Strobe offset in bidirectional memory strobe configurations 有权
标题翻译：双向内存选通配置中的频闪偏移
公开(公告)号：US08493801B2
公开(公告)日：2013-07-23
申请号：US13570430
申请日：2012-08-09
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译：一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

6. 发明申请

US20120300564A1 Strobe Offset in Bidirectional Memory Strobe Configurations 有权
标题翻译：双向内存频闪配置中的频闪偏移
公开(公告)号：US20120300564A1
公开(公告)日：2012-11-29
申请号：US13570430
申请日：2012-08-09
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译：一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

7. 发明授权

US08718216B2 Digital phase detector with zero phase offset 失效
公开(公告)号：US08718216B2
公开(公告)日：2014-05-06
申请号：US13242053
申请日：2011-09-23
申请人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
发明人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
IPC分类号： H03D3/24
CPC分类号： H04L7/0037 , H03L7/0814 , H03L7/085 , H03L7/089
摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

8. 发明授权

US08452919B2 Advanced memory device having improved performance, reduced power and increased reliability 有权
标题翻译：先进的存储器件具有改进的性能，降低的功率和增加的可靠性
公开(公告)号：US08452919B2
公开(公告)日：2013-05-28
申请号：US13567357
申请日：2012-08-06
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G06F13/00
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译：具有改进性能，降低功耗和增加可靠性的高级内存。存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路对错误控制编码电路检测接收到的命令中的错误。另一个存储器件包括可编程序序。另一存储器件包括快速退出自刷新模式。另一种存储装置包括由特征装置控制的自动刷新功能。另一存储器件包括由存储器件的特性控制的自动刷新功能。

9. 发明授权

US08089813B2 Controllable voltage reference driver for a memory system 失效
标题翻译：用于存储系统的可控参考电压驱动器
公开(公告)号：US08089813B2
公开(公告)日：2012-01-03
申请号：US12175555
申请日：2008-07-18
申请人： Daniel M. Dreps
发明人： Daniel M. Dreps
IPC分类号： G11C16/06
CPC分类号： G11C29/02 , G11C5/04 , G11C5/063 , G11C5/147 , G11C8/08 , G11C29/021 , G11C29/028
摘要： A voltage reference driver includes a voltage divider circuit with a voltage reference output node to output a voltage between a first voltage and a second voltage. The voltage reference driver also includes a first selectable impedance circuit coupled to a node at the first voltage and further coupled to the voltage reference output node, and a second selectable impedance circuit coupled to a node at the second voltage and further coupled to the voltage reference output node. Combinations of the first selectable impedance circuit and the second selectable impedance circuit are selectable such that a constant impedance is maintained at the voltage reference output node within a threshold value.
摘要翻译：电压参考驱动器包括具有电压参考输出节点的分压器电路，以输出第一电压和第二电压之间的电压。电压参考驱动器还包括耦合到处于第一电压的节点的第一可选择阻抗电路并进一步耦合到电压参考输出节点，以及第二可选阻抗电路，耦合到处于第二电压的节点，并且还耦合到电压基准输出节点。可选择第一可选择阻抗电路和第二可选择阻抗电路的组合，使得在阈值内的电压参考输出节点处保持恒定的阻抗。

10. 发明申请

US20110289270A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR DATA TRANSFER MANAGEMENT 有权
标题翻译：用于数据传输管理的系统，方法和计算机程序产品
公开(公告)号：US20110289270A1
公开(公告)日：2011-11-24
申请号：US12786072
申请日：2010-05-24
申请人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Daniel M. Dreps , Luis A. Lastras-Montano , Michael Jay Shapiro
发明人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Daniel M. Dreps , Luis A. Lastras-Montano , Michael Jay Shapiro
IPC分类号： G06F17/30 , G06F12/00
CPC分类号： G06F17/30899 , G06F17/30259 , G06K9/6202
摘要： According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.
摘要翻译：根据本公开的一个方面，公开了一种用于管理数据传送的方法和技术。该方法包括将由数据处理系统的处理器单元将要写入存储器子系统的数据与存储的数据模式进行比较，并且响应于确定数据与存储的数据模式匹配，用模式标签替换匹配数据对应于匹配的数据模式。该方法还包括将模式标签发送到存储器子系统。

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